luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fix coppied functions from replica array to work correctly in capped array

This commit is contained in:
samuelkcrow 2023-02-06 19:57:42 -08:00
parent 4a22c5c56f
commit c256a5eb44
2 changed files with 5 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
compiler/modules/capped_replica_bitcell_array.py
View File

@ -541,15 +541,13 @@ class capped_replica_bitcell_array(bitcell_base_array):
""" """
Excludes bits in column from being added to graph except target Excludes bits in column from being added to graph except target
""" """
self.bitcell_array.graph_exclude_bits(targ_row, targ_col) self.replica_bitcell_array.graph_exclude_bits(targ_row, targ_col)
def graph_exclude_replica_col_bits(self): def graph_exclude_replica_col_bits(self):
""" """
Exclude all replica/dummy cells in the replica columns except the replica bit. Exclude all replica/dummy cells in the replica columns except the replica bit.
""" """
self.replica_bitcell_array.graph_exclude_replica_col_bits()
for port in self.left_rbl + self.right_rbl:
self.replica_columns[port].exclude_all_but_replica()
def get_cell_name(self, inst_name, row, col): def get_cell_name(self, inst_name, row, col):
""" """
@ -561,4 +559,4 @@ class capped_replica_bitcell_array(bitcell_base_array):
""" """
Clears the bit exclusions Clears the bit exclusions
""" """
self.bitcell_array.init_graph_params() self.replica_bitcell_array.clear_exclude_bits()

4
compiler/modules/local_bitcell_array.py
View File

@ -163,7 +163,7 @@ class local_bitcell_array(bitcell_base_array):
# FIXME: Replace this with a tech specific parameter # FIXME: Replace this with a tech specific parameter
driver_to_array_spacing = 3 * self.m3_pitch driver_to_array_spacing = 3 * self.m3_pitch
wl_offset = vector(0, self.bitcell_array.get_replica_bottom()) # look for offset problems here wl_offset = vector(0, self.bitcell_array.get_replica_bottom())
self.wl_insts[0].place(wl_offset) self.wl_insts[0].place(wl_offset)
bitcell_array_offset = vector(self.wl_insts[0].rx() + driver_to_array_spacing, 0) bitcell_array_offset = vector(self.wl_insts[0].rx() + driver_to_array_spacing, 0)
@ -171,7 +171,7 @@ class local_bitcell_array(bitcell_base_array):
if len(self.all_ports) > 1: if len(self.all_ports) > 1:
wl_offset = vector(self.bitcell_array_inst.rx() + self.wl_array.width + driver_to_array_spacing, wl_offset = vector(self.bitcell_array_inst.rx() + self.wl_array.width + driver_to_array_spacing,
self.bitcell_array.get_replica_bottom() + self.wl_array.height + self.cell.height) # look for offset problems here self.bitcell_array.get_replica_bottom() + self.wl_array.height + self.cell.height)
self.wl_insts[1].place(wl_offset, self.wl_insts[1].place(wl_offset,
mirror="XY") mirror="XY")