diff --git a/compiler/modules/capped_replica_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py
index c1f9c83f..1814e310 100644
--- a/compiler/modules/capped_replica_bitcell_array.py
+++ b/compiler/modules/capped_replica_bitcell_array.py
@@ -541,15 +541,13 @@ class capped_replica_bitcell_array(bitcell_base_array):
         """
         Excludes bits in column from being added to graph except target
         """
-        self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
+        self.replica_bitcell_array.graph_exclude_bits(targ_row, targ_col)
 
     def graph_exclude_replica_col_bits(self):
         """
         Exclude all replica/dummy cells in the replica columns except the replica bit.
         """
-
-        for port in self.left_rbl + self.right_rbl:
-            self.replica_columns[port].exclude_all_but_replica()
+        self.replica_bitcell_array.graph_exclude_replica_col_bits()
 
     def get_cell_name(self, inst_name, row, col):
         """
@@ -561,4 +559,4 @@ class capped_replica_bitcell_array(bitcell_base_array):
         """
         Clears the bit exclusions
         """
-        self.bitcell_array.init_graph_params()
+        self.replica_bitcell_array.clear_exclude_bits()
diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py
index ef7da9af..b9823e9d 100644
--- a/compiler/modules/local_bitcell_array.py
+++ b/compiler/modules/local_bitcell_array.py
@@ -163,7 +163,7 @@ class local_bitcell_array(bitcell_base_array):
         # FIXME: Replace this with a tech specific parameter
         driver_to_array_spacing = 3 * self.m3_pitch
 
-        wl_offset = vector(0, self.bitcell_array.get_replica_bottom()) # look for offset problems here
+        wl_offset = vector(0, self.bitcell_array.get_replica_bottom())
         self.wl_insts[0].place(wl_offset)
 
         bitcell_array_offset = vector(self.wl_insts[0].rx() + driver_to_array_spacing, 0)
@@ -171,7 +171,7 @@ class local_bitcell_array(bitcell_base_array):
 
         if len(self.all_ports) > 1:
             wl_offset = vector(self.bitcell_array_inst.rx() + self.wl_array.width + driver_to_array_spacing,
-                               self.bitcell_array.get_replica_bottom() + self.wl_array.height + self.cell.height) # look for offset problems here
+                               self.bitcell_array.get_replica_bottom() + self.wl_array.height + self.cell.height)
             self.wl_insts[1].place(wl_offset,
                                    mirror="XY")