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Global bitcell array passes LVS/DRC

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mrg
2020-09-01 10:57:49 -07:00
parent 7bdce3ca9a
commit c1c631abe1
4 changed files with 148 additions and 56 deletions
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compiler/modules/local_bitcell_array.py
+2 -2
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@@ -110,7 +110,7 @@ class local_bitcell_array(design.design):
# word lines (bottom to top)
# vdd
# gnd
self.add_pin_list([x for x in self.all_array_bitline_names if not x.startswith("dummy")], "INOUT")
self.add_pin_list(self.all_array_bitline_names, "INOUT")
for port in self.all_ports:
self.add_pin_list(self.wordline_names[port], "INPUT")
self.add_pin("vdd", "POWER")
@@ -146,7 +146,7 @@ class local_bitcell_array(design.design):
mirror="MY")
self.height = self.bitcell_array.height
self.width = self.bitcell_array_inst.rx()
self.width = max(self.bitcell_array_inst.rx(), max([x.rx() for x in self.wl_insts]))
def route_unused_wordlines(self):
""" Connect the unused RBL and dummy wordlines to gnd """