diff --git a/compiler/modules/global_bitcell_array.py b/compiler/modules/global_bitcell_array.py index 264a3500..d0b051ff 100644 --- a/compiler/modules/global_bitcell_array.py +++ b/compiler/modules/global_bitcell_array.py @@ -10,6 +10,7 @@ from globals import OPTS from sram_factory import factory from vector import vector import debug +from numpy import cumsum class global_bitcell_array(design.design): @@ -19,20 +20,19 @@ class global_bitcell_array(design.design): Cols is a list of the array widths. add_left_rbl and add_right_ """ - def __init__(self, rows, cols, ports, name=""): + def __init__(self, rows, cols, name=""): # The total of all columns will be the number of columns super().__init__(name=name) self.cols = cols + self.num_cols = sum(cols) + self.col_offsets = [0] + list(cumsum(self.cols)[:-1]) self.rows = rows - self.all_ports = ports - debug.check(len(ports)<=2, "Only support dual port or less in global bitcell array.") + debug.check(len(self.all_ports)<=2, "Only support dual port or less in global bitcell array.") self.rbl = [1, 1 if len(self.all_ports)>1 else 0] self.left_rbl = self.rbl[0] self.right_rbl = self.rbl[1] - # Just used for pin names - self.cell = factory.create(module_type="bitcell") self.create_netlist() if not OPTS.netlist_only: @@ -48,6 +48,8 @@ class global_bitcell_array(design.design): self.place() + self.route() + self.add_layout_pins() self.add_boundary() @@ -58,6 +60,12 @@ class global_bitcell_array(design.design): """ Add the modules used in this design """ self.local_mods = [] + if self.cols == 1: + la = factory.create(module_type="local_bitcell_array", rows=self.rows, cols=self.cols[0], rbl=self.rbl, add_rbl=[self.left_rbl, self.right_rbl]) + self.add_mod(la) + self.local_mods.append(la) + return + for i, cols in enumerate(self.cols): # Always add the left RBLs to the first subarray and the right RBLs to the last subarray if i == 0: @@ -69,10 +77,9 @@ class global_bitcell_array(design.design): self.add_mod(la) self.local_mods.append(la) - def add_pins(self): - return + self.add_bitline_pins() self.add_wordline_pins() @@ -80,60 +87,84 @@ class global_bitcell_array(design.design): self.add_pin("gnd", "GROUND") def add_bitline_pins(self): + self.bitline_names = [] for port in self.all_ports: - self.add_pin_list(self.replica_bitline_names[port], "INOUT") + self.bitline_names.append("rbl_bl_{0}_{1}".format(port, 0)) + self.bitline_names.append("rbl_br_{0}_{1}".format(port, 0)) + + for col in range(self.num_cols): + for port in self.all_ports: + self.bitline_names.append("bl_{0}_{1}".format(port, col)) + self.bitline_names.append("br_{0}_{1}".format(port, col)) + + if len(self.all_ports) > 1: + for port in self.all_ports: + self.bitline_names.append("rbl_bl_{0}_{1}".format(port, 1)) + self.bitline_names.append("rbl_br_{0}_{1}".format(port, 1)) + self.add_pin_list(self.bitline_names, "INOUT") def add_wordline_pins(self): - # All wordline names for all ports - self.wordline_names = [] - # Wordline names for each port - self.wordline_names_by_port = [[] for x in self.all_ports] - # Replica wordlines by port - self.replica_wordline_names = [[] for x in self.all_ports] - - # Regular array wordline names - self.bitcell_array_wordline_names = self.bitcell_array.get_all_wordline_names() - self.wordline_names = [] - # Left port WLs - for port in range(self.left_rbl): - # Make names for all RBLs - wl_names=["rbl_{0}_{1}".format(x, port) for x in self.cell.get_all_wl_names()] - # Keep track of the pin that is the RBL - self.replica_wordline_names[port] = wl_names - self.wordline_names.extend(wl_names) + self.wordline_names.append("rbl_wl_0_0") # Regular WLs - self.wordline_names.extend(self.bitcell_array_wordline_names) - - # Right port WLs - for port in range(self.left_rbl, self.left_rbl + self.right_rbl): - # Make names for all RBLs - wl_names=["rbl_{0}_{1}".format(x, port) for x in self.cell.get_all_wl_names()] - # Keep track of the pin that is the RBL - self.replica_wordline_names[port] = wl_names - self.wordline_names.extend(wl_names) - - # Array of all port wl names - for port in range(self.left_rbl + self.right_rbl): - wl_names = ["rbl_{0}_{1}".format(x, port) for x in self.cell.get_all_wl_names()] - self.replica_wordline_names[port] = wl_names + for row in range(self.rows): + for port in self.all_ports: + self.wordline_names.append("wl_{0}_{1}".format(port, row)) + + if len(self.all_ports) > 1: + self.wordline_names.append("rbl_wl_1_1") self.add_pin_list(self.wordline_names, "INPUT") - def create_instances(self): """ Create the module instances used in this design """ + + self.local_insts = [] - for i, mod in enumerate(self.local_mods): - name = "la_{0}".format(i) + for col, mod in zip(self.col_offsets, self.local_mods): + name = "la_{0}".format(col) self.local_insts.append(self.add_inst(name=name, - mod=mod)) - self.connect_inst(mod.pins) + mod=mod)) + + temp = [] + if col == 0: + temp.append("rbl_bl_0_0") + temp.append("rbl_br_0_0") + if len(self.all_ports) > 1: + temp.append("rbl_bl_1_0") + temp.append("rbl_br_1_0") + + port_inouts = [x for x in mod.get_inouts() if x.startswith("bl") or x.startswith("br")] + for pin_name in port_inouts: + # Offset of the last underscore that defines the bit number + bit_index = pin_name.rindex('_') + # col is the bit offset of the local array, + # while col_value is the offset within this array + col_value = int(pin_name[bit_index + 1:]) + # Name of signal without the bit + base_name = pin_name[:bit_index] + # Strip the bit and add the new one + new_name = "{0}_{1}".format(base_name, col + col_value) + temp.append(new_name) + + if len(self.all_ports) > 1 and mod == self.local_mods[-1]: + temp.append("rbl_bl_0_1") + temp.append("rbl_br_0_1") + temp.append("rbl_bl_1_1") + temp.append("rbl_br_1_1") + + for port in self.all_ports: + port_inputs = [x for x in mod.get_inputs() if "wl_{}".format(port) in x] + temp.extend(port_inputs) + + temp.append("vdd") + temp.append("gnd") + self.connect_inst(temp) def place(self): offset = vector(0, 0) @@ -144,5 +175,61 @@ class global_bitcell_array(design.design): self.height = self.local_mods[0].height self.width = self.local_insts[-1].rx() + def route(self): + + # Route the global wordlines (assumes pins all line up) + for port in self.all_ports: + port_inputs = [x for x in self.local_mods[0].get_inputs() if "wl_{}".format(port) in x] + for i, pin_name in enumerate(port_inputs): + pins = [x.get_pin(pin_name) for x in self.local_insts] + + y_offset = pins[0].cy() + if port == 0: + y_offset -= 1.5 * self.m3_pitch + else: + y_offset += 1.5 * self.m3_pitch + + start_offset = vector(pins[0].lx(), y_offset) + end_offset = vector(pins[-1].rx(), y_offset) + self.add_layout_pin_segment_center(text=pin_name, + layer="m3", + start=start_offset, + end=end_offset) + + for pin in pins: + self.add_via_stack_center(from_layer=pin.layer, + to_layer="m3", + offset=pin.center()) + end_offset = vector(pin.cx(), y_offset) + self.add_path("m3", [pin.center(), end_offset]) + def add_layout_pins(self): - pass + + # Regular bitlines + for col, inst in zip(self.col_offsets, self.local_insts): + for port in self.all_ports: + port_inouts = [x for x in inst.mod.get_inouts() if x.startswith("bl_{}".format(port)) or x.startswith("br_{}".format(port))] + for pin_name in port_inouts: + # Offset of the last underscore that defines the bit number + bit_index = pin_name.rindex('_') + # col is the bit offset of the local array, + # while col_value is the offset within this array + col_value = int(pin_name[bit_index + 1:]) + # Name of signal without the bit + base_name = pin_name[:bit_index] + # Strip the bit and add the new one + new_name = "{0}_{1}".format(base_name, col + col_value) + self.copy_layout_pin(inst, pin_name, new_name) + + + # Replica bitlines + self.copy_layout_pin(self.local_insts[0], "rbl_bl_0_0") + self.copy_layout_pin(self.local_insts[0], "rbl_br_0_0") + + if len(self.all_ports) > 1: + self.copy_layout_pin(self.local_insts[-1], "rbl_bl_1_0") + self.copy_layout_pin(self.local_insts[-1], "rbl_br_1_0") + + for inst in self.insts: + self.copy_power_pins(inst, "vdd") + self.copy_power_pins(inst, "gnd") diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index 7a917390..f82b5cd1 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -110,7 +110,7 @@ class local_bitcell_array(design.design): # word lines (bottom to top) # vdd # gnd - self.add_pin_list([x for x in self.all_array_bitline_names if not x.startswith("dummy")], "INOUT") + self.add_pin_list(self.all_array_bitline_names, "INOUT") for port in self.all_ports: self.add_pin_list(self.wordline_names[port], "INPUT") self.add_pin("vdd", "POWER") @@ -146,7 +146,7 @@ class local_bitcell_array(design.design): mirror="MY") self.height = self.bitcell_array.height - self.width = self.bitcell_array_inst.rx() + self.width = max(self.bitcell_array_inst.rx(), max([x.rx() for x in self.wl_insts])) def route_unused_wordlines(self): """ Connect the unused RBL and dummy wordlines to gnd """ diff --git a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py index d92e3b2b..dd17d82e 100755 --- a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py @@ -22,8 +22,13 @@ class global_bitcell_array_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell without replica") - a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4, ports=[0]) + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing 2 x 4x4 global bitcell array for cell_1rw_1r") + a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4) self.local_check(a) # debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column") diff --git a/compiler/tests/15_global_bitcell_array_test.py b/compiler/tests/15_global_bitcell_array_test.py index 18c25c37..ed7e282a 100755 --- a/compiler/tests/15_global_bitcell_array_test.py +++ b/compiler/tests/15_global_bitcell_array_test.py @@ -15,20 +15,20 @@ from sram_factory import factory import debug -@unittest.skip("SKIPPING 05_global_bitcell_array_test") +# @unittest.skip("SKIPPING 05_global_bitcell_array_test") class global_bitcell_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell without replica") - a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4, ports=[0]) - self.local_check(a) - - # debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column") - # a = factory.create(module_type="local_bitcell_array", cols=4, left_rbl=1, rows=4, ports=[0]) + # debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell") + # a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4) # self.local_check(a) + + debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell") + a = factory.create(module_type="global_bitcell_array", cols=[10, 6], rows=4) + self.local_check(a) globals.end_openram()