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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 09:30:38 +02:00
Performed clean up and added comments.
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@@ -700,15 +700,6 @@ class bank(design.design):
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offset=data_pin.center(),
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height=data_pin.height(),
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width=data_pin.width())
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#
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# if self.word_size is not None:
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# for bit in range(self.num_wmasks):
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# wmask_pin = self.port_data_inst[port].get_pin("bank_wmask_{0}".format(bit))
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# self.add_layout_pin_rect_center(text="bank_wmask{0}_{1}".format(port, bit),
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# layer=wmask_pin.layer,
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# offset=wmask_pin.center(),
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# height=wmask_pin.height(),
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# width=wmask_pin.width())
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def route_port_address_in(self, port):
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@@ -459,12 +459,13 @@ class port_data(design.design):
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# the wdriver_sel_{} pin in the write driver AND array.
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spacing = 2*drc("metal2_to_metal2")
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if bit == 0:
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# When the write mask output pin is right of the bitline, the target is found
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while (wmask_out_pin.lx() > inst2.get_pin("data_{0}".format(loc)).rx()):
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loc += 1
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length = inst2.get_pin("data_{0}".format(loc)).rx() + spacing
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else:
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next_loc = loc + ( bit*self.write_size )
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next_loc = loc + (bit * self.write_size)
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length = inst2.get_pin("data_{0}".format(next_loc)).rx() + spacing
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beg_pos = wmask_out_pin.center()
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