From c19bada8df748d631b13b655b2d1afd2ef983d8a Mon Sep 17 00:00:00 2001 From: jsowash Date: Mon, 19 Aug 2019 08:57:05 -0700 Subject: [PATCH] Performed clean up and added comments. --- compiler/modules/bank.py | 9 --------- compiler/modules/port_data.py | 3 ++- compiler/sram/sram_1bank.py | 37 ++++++++++++++++------------------- 3 files changed, 19 insertions(+), 30 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 445cafc9..7d14f601 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -700,15 +700,6 @@ class bank(design.design): offset=data_pin.center(), height=data_pin.height(), width=data_pin.width()) - # - # if self.word_size is not None: - # for bit in range(self.num_wmasks): - # wmask_pin = self.port_data_inst[port].get_pin("bank_wmask_{0}".format(bit)) - # self.add_layout_pin_rect_center(text="bank_wmask{0}_{1}".format(port, bit), - # layer=wmask_pin.layer, - # offset=wmask_pin.center(), - # height=wmask_pin.height(), - # width=wmask_pin.width()) def route_port_address_in(self, port): diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index bd9b5069..3132cc86 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -459,12 +459,13 @@ class port_data(design.design): # the wdriver_sel_{} pin in the write driver AND array. spacing = 2*drc("metal2_to_metal2") if bit == 0: + # When the write mask output pin is right of the bitline, the target is found while (wmask_out_pin.lx() > inst2.get_pin("data_{0}".format(loc)).rx()): loc += 1 length = inst2.get_pin("data_{0}".format(loc)).rx() + spacing else: - next_loc = loc + ( bit*self.write_size ) + next_loc = loc + (bit * self.write_size) length = inst2.get_pin("data_{0}".format(next_loc)).rx() + spacing beg_pos = wmask_out_pin.center() diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index b3f6983f..7725cd3b 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -94,7 +94,7 @@ class sram_1bank(sram_base): if self.write_size is not None: if port in self.write_ports: wmask_pos[port] = vector(self.bank.bank_array_ll.x, - - 2*max_gap_size - 2*self.dff.height) + - 1.5*max_gap_size - 2*self.dff.height) self.wmask_dff_insts[port].place(wmask_pos[port]) else: wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0) @@ -135,15 +135,6 @@ class sram_1bank(sram_base): -max_gap_size - self.data_dff_insts[port].height) self.data_dff_insts[port].place(data_pos[port]) - # # Add the write mask flops below the din flops. - # if self.write_size is not None: - # if port in self.write_ports: - # wmask_pos[port] = vector(self.bank.bank_array_ll.x, - # -max_gap_size - self.wmask_dff_insts[port].height) - # # wmask_pos[port] = vector(self.bank.bank_array_ll.x - self.control_logic_insts[port].width, - # # -max_gap_size - self.wmask_dff_insts[port].height) - # self.wmask_dff_insts[port].place(wmask_pos[port]) - if len(self.all_ports)>1: # Port 1 @@ -163,7 +154,7 @@ class sram_1bank(sram_base): if self.write_size is not None: if port in self.write_ports: wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - self.bank.height + 2*max_gap_size + 2*self.dff.height) + self.bank.height + 1.5*max_gap_size + 2*self.dff.height) self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX") # Add the write mask flops to the left of the din flops. @@ -208,14 +199,6 @@ class sram_1bank(sram_base): self.bank.height + max_gap_size + self.dff.height) self.data_dff_insts[port].place(data_pos[port], mirror="MX") - # # Add the write mask flops to the left of the din flops. - # if self.write_size is not None: - # if port in self.write_ports: - # wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - # self.bank.height + max_gap_size + self.data_dff_insts[port].height) - # self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX") - # - def add_layout_pins(self): """ Add the top-level pins for a single bank SRAM with control. @@ -412,11 +395,25 @@ class sram_1bank(sram_base): dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)] dff_pins = [self.wmask_dff_insts[port].get_pin(x) for x in dff_names] + for x in dff_names: + self.add_via_center(layers=("metal1", "via1", "metal2"), + offset=self.wmask_dff_insts[port].get_pin(x).center()) + self.add_via_center(layers=("metal2", "via2", "metal3"), + offset=self.wmask_dff_insts[port].get_pin(x).center()) + bank_names = ["bank_wmask{0}_{1}".format(port, x) for x in range(self.num_wmasks)] bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] + for x in bank_names: + self.add_via_center(layers=("metal1", "via1", "metal2"), + offset=self.bank_inst.get_pin(x).center()) + self.add_via_center(layers=("metal2", "via2", "metal3"), + offset=self.bank_inst.get_pin(x).center()) + route_map = list(zip(bank_pins, dff_pins)) - self.create_horizontal_channel_route(route_map, offset) + self.create_horizontal_channel_route(netlist=route_map, + offset=offset, + layer_stack=("metal3", "via3", "metal4")) def add_lvs_correspondence_points(self):