diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py
index 932306da..a46ccebf 100644
--- a/compiler/modules/sense_amp_array.py
+++ b/compiler/modules/sense_amp_array.py
@@ -28,7 +28,7 @@ class sense_amp_array(design.design):
 
         self.word_size = word_size
         self.words_per_row = words_per_row
-        self.columns = word_size * words_per_row
+        self.num_cols = word_size * words_per_row
         self.offsets = offsets
         if not num_spare_cols:
             self.num_spare_cols = 0
@@ -121,7 +121,7 @@ class sense_amp_array(design.design):
             for i in range(self.num_cols + self.num_spare_cols):
                 self.offsets.append(i * self.bitcell.width)
 
-        for i, xoffset in enumerate(self.offsets[0:self.columns:self.words_per_row]):
+        for i, xoffset in enumerate(self.offsets[0:self.num_cols:self.words_per_row]):
             if cell_properties.bitcell.mirror.y and (i * self.words_per_row + self.column_offset) % 2:
                 mirror = "MY"
                 xoffset = xoffset + self.amp_spacing
@@ -132,7 +132,7 @@ class sense_amp_array(design.design):
             self.local_insts[i].place(offset=amp_position, mirror=mirror)
             
         # place spare sense amps (will share the same enable as regular sense amps)
-        for i, xoffset in enumerate(self.offsets[self.columns:]):
+        for i, xoffset in enumerate(self.offsets[self.num_cols:]):
             index = self.word_size + i
             if cell_properties.bitcell.mirror.y and (index + self.column_offset) % 2:
                 mirror = "MY"
diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py
index 3de81888..d505fbc2 100644
--- a/compiler/modules/write_driver_array.py
+++ b/compiler/modules/write_driver_array.py
@@ -70,7 +70,7 @@ class write_driver_array(design.design):
 
         self.place_write_array()
         self.width = self.driver_insts[-1].rx()
-        self.width_regular_cols = self.driver_insts[-self.num_spare_cols].rx()
+        self.width_regular_cols = self.driver_insts[-self.num_spare_cols].lx()
         self.height = self.driver.height
         self.add_layout_pins()
         self.add_boundary()
@@ -252,7 +252,7 @@ class write_driver_array(design.design):
                 en_pin = inst.get_pin(inst.mod.en_name)
                 self.add_layout_pin(text=self.en_name + "_{0}".format(i + 1),
                                     layer="m1",
-                                    offset=en_pin.lr() + vector(-drc("minwidth_m1"),0))
+                                    offset=en_pin.lr() + vector(-drc("minwidth_m1"), 0))
 
         else:
             inst = self.driver_insts[0]