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Add dff_buf and dff_array modules.

This commit is contained in:
Matt Guthaus 2018-03-05 16:24:54 -08:00
parent a2514878c1
commit c020d74f26
3 changed files with 6 additions and 7 deletions
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10
compiler/modules/dff_array.py
View File

@ -62,9 +62,9 @@ class dff_array(design.design):
mod=self.dff,
offset=base,
mirror=mirror)
self.connect_inst(["din[{0}][{1}]".format(x,y),
"dout[{0}][{1}]".format(x,y),
"dout_bar[{0}][{1}]".format(x,y),
self.connect_inst([self.get_din_name(y,x),
self.get_dout_name(y,x),
self.get_dout_bar_name(y,x),
"clk",
"vdd",
"gnd"])
@ -159,7 +159,7 @@ class dff_array(design.design):
else:
self.add_layout_pin(text="clk",
layer="metal3",
offset=clk_pin.ll().scale(0,1),
offset=vector(0,0),
width=self.width,
height=self.m3_width)
for x in range(self.columns):
@ -172,7 +172,7 @@ class dff_array(design.design):
height=self.height)
# Drop a via to the M3 pin
self.add_via_center(layers=("metal2","via2","metal3"),
offset=clk_pin.center())
offset=clk_pin.center().scale(1,0))

3
compiler/modules/dff_buf.py
View File

@ -86,8 +86,7 @@ class dff_buf(design.design):
z1_pin = self.inv1_inst.get_pin("Z")
a2_pin = self.inv2_inst.get_pin("A")
mid_point = vector(z1_pin.cx(), a2_pin.cy())
self.add_wire(("metal1","via1","metal2"),
[z1_pin.center(), mid_point, a2_pin.center()])
self.add_path("metal1", [z1_pin.center(), mid_point, a2_pin.center()])
def add_layout_pins(self):

BIN
technology/freepdk45/gds_lib/dff.gds
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