diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 6673a130..293044b2 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -62,9 +62,9 @@ class dff_array(design.design): mod=self.dff, offset=base, mirror=mirror) - self.connect_inst(["din[{0}][{1}]".format(x,y), - "dout[{0}][{1}]".format(x,y), - "dout_bar[{0}][{1}]".format(x,y), + self.connect_inst([self.get_din_name(y,x), + self.get_dout_name(y,x), + self.get_dout_bar_name(y,x), "clk", "vdd", "gnd"]) @@ -159,7 +159,7 @@ class dff_array(design.design): else: self.add_layout_pin(text="clk", layer="metal3", - offset=clk_pin.ll().scale(0,1), + offset=vector(0,0), width=self.width, height=self.m3_width) for x in range(self.columns): @@ -172,7 +172,7 @@ class dff_array(design.design): height=self.height) # Drop a via to the M3 pin self.add_via_center(layers=("metal2","via2","metal3"), - offset=clk_pin.center()) + offset=clk_pin.center().scale(1,0)) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 6d214e6e..29ad3802 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -86,8 +86,7 @@ class dff_buf(design.design): z1_pin = self.inv1_inst.get_pin("Z") a2_pin = self.inv2_inst.get_pin("A") mid_point = vector(z1_pin.cx(), a2_pin.cy()) - self.add_wire(("metal1","via1","metal2"), - [z1_pin.center(), mid_point, a2_pin.center()]) + self.add_path("metal1", [z1_pin.center(), mid_point, a2_pin.center()]) def add_layout_pins(self): diff --git a/technology/freepdk45/gds_lib/dff.gds b/technology/freepdk45/gds_lib/dff.gds index db7d3af3..526a1861 100644 Binary files a/technology/freepdk45/gds_lib/dff.gds and b/technology/freepdk45/gds_lib/dff.gds differ