mirror of https://github.com/VLSIDA/OpenRAM.git
Add dff_buf and dff_array modules.
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@ -62,9 +62,9 @@ class dff_array(design.design):
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mod=self.dff,
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mod=self.dff,
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offset=base,
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offset=base,
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mirror=mirror)
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mirror=mirror)
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self.connect_inst(["din[{0}][{1}]".format(x,y),
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self.connect_inst([self.get_din_name(y,x),
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"dout[{0}][{1}]".format(x,y),
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self.get_dout_name(y,x),
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"dout_bar[{0}][{1}]".format(x,y),
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self.get_dout_bar_name(y,x),
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"clk",
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"clk",
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"vdd",
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"vdd",
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"gnd"])
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"gnd"])
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@ -159,7 +159,7 @@ class dff_array(design.design):
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else:
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else:
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self.add_layout_pin(text="clk",
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self.add_layout_pin(text="clk",
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layer="metal3",
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layer="metal3",
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offset=clk_pin.ll().scale(0,1),
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offset=vector(0,0),
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width=self.width,
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width=self.width,
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height=self.m3_width)
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height=self.m3_width)
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for x in range(self.columns):
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for x in range(self.columns):
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@ -172,7 +172,7 @@ class dff_array(design.design):
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height=self.height)
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height=self.height)
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# Drop a via to the M3 pin
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# Drop a via to the M3 pin
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self.add_via_center(layers=("metal2","via2","metal3"),
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=clk_pin.center())
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offset=clk_pin.center().scale(1,0))
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@ -86,8 +86,7 @@ class dff_buf(design.design):
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z1_pin = self.inv1_inst.get_pin("Z")
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z1_pin = self.inv1_inst.get_pin("Z")
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a2_pin = self.inv2_inst.get_pin("A")
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a2_pin = self.inv2_inst.get_pin("A")
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mid_point = vector(z1_pin.cx(), a2_pin.cy())
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mid_point = vector(z1_pin.cx(), a2_pin.cy())
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self.add_wire(("metal1","via1","metal2"),
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self.add_path("metal1", [z1_pin.center(), mid_point, a2_pin.center()])
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[z1_pin.center(), mid_point, a2_pin.center()])
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def add_layout_pins(self):
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def add_layout_pins(self):
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