mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'dev' into fix_rbl_cell_connections
This commit is contained in:
Matt Guthaus
commit
c01f0f5274
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@ -0,0 +1,23 @@
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import design
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import debug
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import utils
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from tech import GDS,layer
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class replica_bitcell_1rw_1r(design.design):
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"""
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A single bit cell which is forced to store a 0.
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This module implements the single memory cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library. """
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pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("replica_cell_1rw_1r", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "replica_cell_1rw_1r", GDS["unit"], layer["boundary"])
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def __init__(self):
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design.design.__init__(self, "replica_cell_1rw_1r")
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debug.info(2, "Create replica bitcell 1rw+1r object")
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self.width = replica_bitcell_1rw_1r.width
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self.height = replica_bitcell_1rw_1r.height
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self.pin_map = replica_bitcell_1rw_1r.pin_map
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@ -36,6 +36,14 @@ class functional(simulation):
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self.write_check = []
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self.read_check = []
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def set_spice_constants(self):
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"""Spice constants for functional test"""
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simulation.set_spice_constants(self)
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#Heuristic increase for functional period. Base feasible period typically does not pass the functional test
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#for column mux of this size. Increase the feasible period by 20% for this case.
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if self.sram.words_per_row >= 4:
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self.period = self.period*1.2
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def run(self):
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# Generate a random sequence of reads and writes
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self.write_random_memory_sequence()
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@ -208,14 +208,14 @@ class simulation():
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t_current,
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t_current+self.period)
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elif op == "write":
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comment = "\tWriting {0} to address {1} (from port {2}) during cylce {3} ({4}ns - {5}ns)".format(word,
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comment = "\tWriting {0} to address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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port,
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int(t_current/self.period),
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t_current,
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t_current+self.period)
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else:
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comment = "\tReading {0} from address {1} (from port {2}) during cylce {3} ({4}ns - {5}ns)".format(word,
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comment = "\tReading {0} from address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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port,
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int(t_current/self.period),
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@ -18,13 +18,14 @@ class control_logic(design.design):
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Dynamically generated Control logic for the total SRAM circuit.
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"""
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def __init__(self, num_rows, port_type="rw"):
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def __init__(self, num_rows, words_per_row, port_type="rw"):
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""" Constructor """
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name = "control_logic_" + port_type
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(name))
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self.num_rows = num_rows
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self.words_per_row = words_per_row
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self.port_type = port_type
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if self.port_type == "rw":
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@ -92,13 +93,24 @@ class control_logic(design.design):
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from importlib import reload
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c = reload(__import__(OPTS.replica_bitline))
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replica_bitline = getattr(c, OPTS.replica_bitline)
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# FIXME: These should be tuned according to the size!
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delay_stages = 4 # Must be non-inverting
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delay_fanout = 3 # This can be anything >=2
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delay_stages, delay_fanout = self.get_delay_chain_size()
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bitcell_loads = int(math.ceil(self.num_rows / 2.0))
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self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads, name="replica_bitline_"+self.port_type)
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self.add_mod(self.replica_bitline)
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def get_delay_chain_size(self):
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"""Determine the size of the delay chain used for the Sense Amp Enable """
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# FIXME: These should be tuned according to the additional size parameters
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delay_fanout = 3 # This can be anything >=2
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# Delay stages Must be non-inverting
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if self.words_per_row >= 8:
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delay_stages = 8
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elif self.words_per_row == 4:
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delay_stages = 6
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else:
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delay_stages = 4
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return (delay_stages, delay_fanout)
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def setup_signal_busses(self):
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""" Setup bus names, determine the size of the busses etc """
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@ -189,15 +189,65 @@ class replica_bitline(design.design):
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if pin.layer != "metal1":
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continue
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self.add_path("metal1", [pin_right, pin_extension])
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pin_width_ydir = pin.uy()-pin.by()
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#Width is set to pin y width to avoid DRC issues with m1 gaps
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self.add_path("metal1", [pin_right, pin_extension], pin_width_ydir)
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self.add_power_pin("gnd", pin_extension)
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# for multiport, need to short wordlines to each other so they all connect to gnd
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# for multiport, need to short wordlines to each other so they all connect to gnd.
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wl_last = self.wl_list[self.total_ports-1]+"_{}".format(row)
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pin_last = self.rbl_inst.get_pin(wl_last)
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self.short_wordlines(pin, pin_last, "right", False, row, vector(self.m3_pitch,0))
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def short_wordlines(self, wl_pin_a, wl_pin_b, pin_side, is_replica_cell, cell_row=0, offset_x_vec=None):
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"""Connects the word lines together for a single bitcell. Also requires which side of the bitcell to short the pins."""
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#Assumes input pins are wordlines. Also assumes the word lines are horizontal in metal1. Also assumes pins have same x coord.
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#This is my (Hunter) first time editing layout in openram so this function is likely not optimal.
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if self.total_ports > 1:
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#1. Create vertical metal for all the bitlines to connect to
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#m1 needs to be extended in the y directions, direction needs to be determined as every other cell is flipped
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correct_y = vector(0, 0.5*drc("minwidth_metal1"))
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#x spacing depends on the side being drawn. Unknown to me (Hunter) why the size of the space differs by the side.
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#I assume this is related to how a wire is draw, but I have not investigated the issue.
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if pin_side == "right":
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correct_x = vector(0.5*drc("minwidth_metal1"), 0)
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if offset_x_vec != None:
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correct_x = offset_x_vec
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else:
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correct_x = vector(1.5*drc("minwidth_metal1"), 0)
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if wl_pin_a.uy() > wl_pin_b.uy():
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self.add_path("metal1", [wl_pin_a.rc()+correct_x+correct_y, wl_pin_b.rc()+correct_x-correct_y])
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else:
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self.add_path("metal1", [wl_pin_a.rc()+correct_x-correct_y, wl_pin_b.rc()+correct_x+correct_y])
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elif pin_side == "left":
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if offset_x_vec != None:
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correct_x = offset_x_vec
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else:
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correct_x = vector(1.5*drc("minwidth_metal1"), 0)
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if wl_pin_a.uy() > wl_pin_b.uy():
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self.add_path("metal1", [wl_pin_a.lc()-correct_x+correct_y, wl_pin_b.lc()-correct_x-correct_y])
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else:
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self.add_path("metal1", [wl_pin_a.lc()-correct_x-correct_y, wl_pin_b.lc()-correct_x+correct_y])
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else:
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debug.error("Could not connect wordlines on specified input side={}".format(pin_side),1)
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#2. Connect word lines horizontally. Only replica cell needs. Bitline loads currently already do this.
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for port in range(self.total_ports):
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if is_replica_cell:
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wl = self.wl_list[port]
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pin = self.rbc_inst.get_pin(wl)
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else:
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wl = self.wl_list[port]+"_{}".format(cell_row)
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pin = self.rbl_inst.get_pin(wl)
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if pin_side == "left":
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self.add_path("metal1", [pin.lc()-correct_x, pin.lc()])
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elif pin_side == "right":
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self.add_path("metal1", [pin.rc()+correct_x, pin.rc()])
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correct = vector(0.5*drc("minwidth_metal1"), 0)
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self.add_path("metal1", [pin.rc()-correct, pin_last.rc()-correct])
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def route_supplies(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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@ -217,8 +267,13 @@ class replica_bitline(design.design):
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# Replica bitcell needs to be routed up to M3
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pin=self.rbc_inst.get_pin("vdd")
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# Don't rotate this via to vit in FreePDK45
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self.add_power_pin("vdd", pin.center(), rotate=0)
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# Don't rotate this via to vit in FreePDK45. In the custom cell, the pin cannot be placed
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# directly on vdd or there will be a drc error with a wordline. Place the pin slightly farther
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# away then route to it. A better solution would be to rotate the m1 in the via or move the pin
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# a m1_pitch below the entire cell.
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pin_extension = pin.center() - vector(0,self.m1_pitch)
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self.add_power_pin("vdd", pin_extension, rotate=0)
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self.add_path("metal1", [pin.center(), pin_extension])
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for pin in self.rbc_inst.get_pins("gnd"):
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self.add_power_pin("gnd", pin.center())
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@ -267,9 +322,10 @@ class replica_bitline(design.design):
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wl_last = self.wl_list[self.total_ports-1]
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pin = self.rbc_inst.get_pin(wl)
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pin_last = self.rbc_inst.get_pin(wl_last)
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x_offset = self.short_wordlines(pin, pin_last, "left", True)
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correct = vector(0.5*drc("minwidth_metal1"), 0)
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self.add_path("metal1", [pin.lc()+correct, pin_last.lc()+correct])
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#correct = vector(0.5*drc("minwidth_metal1"), 0)
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#self.add_path("metal1", [pin.lc()+correct, pin_last.lc()+correct])
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# DRAIN ROUTE
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# Route the drain to the vdd rail
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@ -25,6 +25,7 @@ class sense_amp(design.design):
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def input_load(self):
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#Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
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from tech import spice, parameter
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bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file.
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return spice["min_tx_drain_c"]*(bitline_pmos_size/parameter["min_tx_size"])#ff
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@ -218,7 +218,7 @@ class single_level_column_mux_array(design.design):
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rotate=90)
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def analytical_delay(self, vdd, slew, load=0.0):
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from tech import spice
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from tech import spice, parameter
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r = spice["min_tx_r"]/(self.mux.ptx_width/parameter["min_tx_size"])
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#Drains of mux transistors make up capacitance.
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c_para = spice["min_tx_drain_c"]*(self.mux.ptx_width/parameter["min_tx_size"])*self.words_per_row#ff
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@ -223,13 +223,13 @@ class sram_base(design):
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from control_logic import control_logic
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# Create the control logic module for each port type
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if OPTS.num_rw_ports>0:
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self.control_logic = self.control_logic_rw = control_logic(num_rows=self.num_rows, port_type="rw")
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self.control_logic = self.control_logic_rw = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, port_type="rw")
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self.add_mod(self.control_logic_rw)
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if OPTS.num_w_ports>0:
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self.control_logic_w = control_logic(num_rows=self.num_rows, port_type="w")
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self.control_logic_w = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, port_type="w")
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self.add_mod(self.control_logic_w)
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if OPTS.num_r_ports>0:
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self.control_logic_r = control_logic(num_rows=self.num_rows, port_type="r")
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self.control_logic_r = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, port_type="r")
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self.add_mod(self.control_logic_r)
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# Create the address and control flops (but not the clk)
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@ -24,6 +24,7 @@ class replica_bitline_test(openram_test):
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debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = replica_bitline.replica_bitline(stages,fanout,rows)
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self.local_check(a)
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#debug.error("Exiting...", 1)
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stages=8
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rows=100
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@ -31,7 +32,26 @@ class replica_bitline_test(openram_test):
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a = replica_bitline.replica_bitline(stages,fanout,rows)
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self.local_check(a)
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# check replica bitline in multi-port
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#check replica bitline in handmade multi-port 1rw+1r cell
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OPTS.bitcell = "bitcell_1rw_1r"
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OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 1
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stages=4
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fanout=4
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rows=13
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debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = replica_bitline.replica_bitline(stages,fanout,rows)
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self.local_check(a)
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stages=8
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rows=100
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debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = replica_bitline.replica_bitline(stages,fanout,rows)
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self.local_check(a)
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# check replica bitline in pbitcell multi-port
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell = "replica_pbitcell"
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OPTS.num_rw_ports = 1
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|
|
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@ -20,7 +20,7 @@ class control_logic_test(openram_test):
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# check control logic for single port
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debug.info(1, "Testing sample for control_logic")
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a = control_logic.control_logic(num_rows=128)
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a = control_logic.control_logic(num_rows=128, words_per_row=1)
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self.local_check(a)
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# check control logic for multi-port
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@ -31,7 +31,7 @@ class control_logic_test(openram_test):
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OPTS.num_r_ports = 0
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debug.info(1, "Testing sample for control_logic for multiport")
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a = control_logic.control_logic(num_rows=128)
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a = control_logic.control_logic(num_rows=128, words_per_row=1)
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self.local_check(a)
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# Check port specific control logic
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|
|
@ -40,15 +40,15 @@ class control_logic_test(openram_test):
|
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OPTS.num_r_ports = 1
|
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debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
|
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a = control_logic.control_logic(num_rows=128, port_type="rw")
|
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a = control_logic.control_logic(num_rows=128, words_per_row=1, port_type="rw")
|
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self.local_check(a)
|
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|
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debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
|
||||
a = control_logic.control_logic(num_rows=128, port_type="w")
|
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a = control_logic.control_logic(num_rows=128, words_per_row=1, port_type="w")
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for control_logic for multiport, only read control logic")
|
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a = control_logic.control_logic(num_rows=128, port_type="r")
|
||||
a = control_logic.control_logic(num_rows=128, words_per_row=1, port_type="r")
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
|
|
|||
|
|
@ -20,6 +20,9 @@ class psram_1bank_2mux_func_test(openram_test):
|
|||
OPTS.netlist_only = True
|
||||
OPTS.bitcell = "pbitcell"
|
||||
OPTS.replica_bitcell="replica_pbitcell"
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_r_ports = 1
|
||||
OPTS.num_w_ports = 1
|
||||
|
||||
# This is a hack to reload the characterizer __init__ with the spice version
|
||||
from importlib import reload
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ import globals
|
|||
from globals import OPTS
|
||||
import debug
|
||||
|
||||
@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test")
|
||||
#@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test")
|
||||
class psram_1bank_4mux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
@ -20,6 +20,9 @@ class psram_1bank_4mux_func_test(openram_test):
|
|||
OPTS.netlist_only = True
|
||||
OPTS.bitcell = "pbitcell"
|
||||
OPTS.replica_bitcell="replica_pbitcell"
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_r_ports = 1
|
||||
OPTS.num_w_ports = 1
|
||||
|
||||
# This is a hack to reload the characterizer __init__ with the spice version
|
||||
from importlib import reload
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ import globals
|
|||
from globals import OPTS
|
||||
import debug
|
||||
|
||||
@unittest.skip("SKIPPING 22_psram_1bank_8mux_func_test")
|
||||
#@unittest.skip("SKIPPING 22_psram_1bank_8mux_func_test")
|
||||
class psram_1bank_8mux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
@ -20,6 +20,9 @@ class psram_1bank_8mux_func_test(openram_test):
|
|||
OPTS.netlist_only = True
|
||||
OPTS.bitcell = "pbitcell"
|
||||
OPTS.replica_bitcell="replica_pbitcell"
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_r_ports = 1
|
||||
OPTS.num_w_ports = 1
|
||||
|
||||
# This is a hack to reload the characterizer __init__ with the spice version
|
||||
from importlib import reload
|
||||
|
|
@ -29,7 +32,7 @@ class psram_1bank_8mux_func_test(openram_test):
|
|||
from sram import sram
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=4,
|
||||
num_words=512,
|
||||
num_words=256,
|
||||
num_banks=1)
|
||||
c.words_per_row=8
|
||||
debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
|
||||
|
|
|
|||
|
|
@ -20,6 +20,9 @@ class psram_1bank_nomux_func_test(openram_test):
|
|||
OPTS.netlist_only = True
|
||||
OPTS.bitcell = "pbitcell"
|
||||
OPTS.replica_bitcell="replica_pbitcell"
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_r_ports = 1
|
||||
OPTS.num_w_ports = 1
|
||||
|
||||
# This is a hack to reload the characterizer __init__ with the spice version
|
||||
from importlib import reload
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ import globals
|
|||
from globals import OPTS
|
||||
import debug
|
||||
|
||||
@unittest.skip("SKIPPING 22_sram_1bank_4mux_func_test")
|
||||
#@unittest.skip("SKIPPING 22_sram_1bank_4mux_func_test")
|
||||
class sram_1bank_4mux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ import globals
|
|||
from globals import OPTS
|
||||
import debug
|
||||
|
||||
@unittest.skip("SKIPPING 22_sram_1bank_8mux_func_test")
|
||||
#@unittest.skip("SKIPPING 22_sram_1bank_8mux_func_test")
|
||||
class sram_1bank_8mux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
@ -30,7 +30,7 @@ class sram_1bank_8mux_func_test(openram_test):
|
|||
from sram import sram
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=4,
|
||||
num_words=512,
|
||||
num_words=256,
|
||||
num_banks=1)
|
||||
c.words_per_row=8
|
||||
debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
|
||||
|
|
@ -39,6 +39,7 @@ class sram_1bank_8mux_func_test(openram_test):
|
|||
c.num_banks))
|
||||
s = sram(c, name="sram")
|
||||
tempspice = OPTS.openram_temp + "temp.sp"
|
||||
tempspice = OPTS.openram_temp + "temp.sp"
|
||||
s.sp_write(tempspice)
|
||||
|
||||
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
#!/usr/bin/env python3
|
||||
"""
|
||||
Run a functioal test on 1 bank SRAM
|
||||
"""
|
||||
|
||||
import unittest
|
||||
from testutils import header,openram_test
|
||||
import sys,os
|
||||
sys.path.append(os.path.join(sys.path[0],".."))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
import debug
|
||||
|
||||
#@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test")
|
||||
class psram_1bank_nomux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.bitcell = "bitcell_1rw_1r"
|
||||
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_w_ports = 0
|
||||
OPTS.num_r_ports = 1
|
||||
|
||||
# This is a hack to reload the characterizer __init__ with the spice version
|
||||
from importlib import reload
|
||||
import characterizer
|
||||
reload(characterizer)
|
||||
from characterizer import functional
|
||||
from sram import sram
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=4,
|
||||
num_words=32,
|
||||
num_banks=1)
|
||||
c.words_per_row=1
|
||||
debug.info(1, "Functional test for sram 1rw,1r with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
|
||||
c.num_words,
|
||||
c.words_per_row,
|
||||
c.num_banks))
|
||||
s = sram(c, name="sram")
|
||||
tempspice = OPTS.openram_temp + "temp.sp"
|
||||
s.sp_write(tempspice)
|
||||
|
||||
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
|
||||
|
||||
f = functional(s.s, tempspice, corner)
|
||||
f.num_cycles = 10
|
||||
(fail, error) = f.run()
|
||||
self.assertTrue(fail,error)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
# instantiate a copy of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main()
|
||||
Binary file not shown.
|
|
@ -0,0 +1,14 @@
|
|||
|
||||
.SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
|
||||
MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
|
||||
MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
|
||||
MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1
|
||||
MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
|
||||
MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
|
||||
MM4 vdd wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
|
||||
MM1 Q vdd gnd gnd NMOS_VTG W=270.0n L=50n m=1
|
||||
MM0 vdd Q gnd gnd NMOS_VTG W=270.0n L=50n m=1
|
||||
MM3 Q vdd vdd vdd PMOS_VTG W=90n L=50n m=1
|
||||
MM2 vdd Q vdd vdd PMOS_VTG W=90n L=50n m=1
|
||||
.ENDS
|
||||
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -1,6 +1,6 @@
|
|||
magic
|
||||
tech scmos
|
||||
timestamp 1540504134
|
||||
timestamp 1541193956
|
||||
<< nwell >>
|
||||
rect 0 50 54 79
|
||||
<< pwell >>
|
||||
|
|
@ -139,10 +139,10 @@ rect 0 0 54 74
|
|||
<< labels >>
|
||||
rlabel metal1 27 4 27 4 1 wl1
|
||||
rlabel psubstratepcontact 27 11 27 11 1 gnd
|
||||
rlabel m2contact 27 74 27 74 5 vdd
|
||||
rlabel metal1 19 67 19 67 1 wl0
|
||||
rlabel metal2 4 7 4 7 2 bl0
|
||||
rlabel metal2 11 7 11 7 1 bl1
|
||||
rlabel metal2 43 7 43 7 1 br1
|
||||
rlabel metal2 50 7 50 7 8 br0
|
||||
rlabel metal1 19 74 19 74 5 vdd
|
||||
<< end >>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,149 @@
|
|||
magic
|
||||
tech scmos
|
||||
timestamp 1541194096
|
||||
<< nwell >>
|
||||
rect 0 50 54 79
|
||||
<< pwell >>
|
||||
rect 0 0 54 50
|
||||
<< ntransistor >>
|
||||
rect 14 35 16 41
|
||||
rect 22 29 24 41
|
||||
rect 30 29 32 41
|
||||
rect 38 35 40 41
|
||||
rect 14 17 16 25
|
||||
rect 22 17 24 25
|
||||
rect 30 17 32 25
|
||||
rect 38 17 40 25
|
||||
<< ptransistor >>
|
||||
rect 22 58 24 62
|
||||
rect 30 58 32 62
|
||||
<< ndiffusion >>
|
||||
rect 9 39 14 41
|
||||
rect 13 35 14 39
|
||||
rect 16 35 17 41
|
||||
rect 21 33 22 41
|
||||
rect 17 29 22 33
|
||||
rect 24 29 25 41
|
||||
rect 29 29 30 41
|
||||
rect 32 33 33 41
|
||||
rect 37 35 38 41
|
||||
rect 40 39 45 41
|
||||
rect 40 35 41 39
|
||||
rect 32 29 37 33
|
||||
rect 9 23 14 25
|
||||
rect 13 19 14 23
|
||||
rect 9 17 14 19
|
||||
rect 16 17 22 25
|
||||
rect 24 17 25 25
|
||||
rect 29 17 30 25
|
||||
rect 32 17 38 25
|
||||
rect 40 23 45 25
|
||||
rect 40 19 41 23
|
||||
rect 40 17 45 19
|
||||
<< pdiffusion >>
|
||||
rect 21 58 22 62
|
||||
rect 24 58 25 62
|
||||
rect 29 58 30 62
|
||||
rect 32 58 33 62
|
||||
<< ndcontact >>
|
||||
rect 9 35 13 39
|
||||
rect 17 33 21 41
|
||||
rect 25 29 29 41
|
||||
rect 33 33 37 41
|
||||
rect 41 35 45 39
|
||||
rect 9 19 13 23
|
||||
rect 25 17 29 25
|
||||
rect 41 19 45 23
|
||||
<< pdcontact >>
|
||||
rect 17 58 21 62
|
||||
rect 25 58 29 62
|
||||
rect 33 58 37 62
|
||||
<< psubstratepcontact >>
|
||||
rect 25 9 29 13
|
||||
<< nsubstratencontact >>
|
||||
rect 25 72 29 76
|
||||
<< polysilicon >>
|
||||
rect 22 62 24 64
|
||||
rect 30 62 32 64
|
||||
rect 22 48 24 58
|
||||
rect 30 55 32 58
|
||||
rect 31 51 32 55
|
||||
rect 14 41 16 46
|
||||
rect 22 44 23 48
|
||||
rect 22 41 24 44
|
||||
rect 30 41 32 51
|
||||
rect 38 41 40 46
|
||||
rect 14 33 16 35
|
||||
rect 38 33 40 35
|
||||
rect 14 25 16 26
|
||||
rect 22 25 24 29
|
||||
rect 30 25 32 29
|
||||
rect 38 25 40 26
|
||||
rect 14 15 16 17
|
||||
rect 22 15 24 17
|
||||
rect 30 15 32 17
|
||||
rect 38 15 40 17
|
||||
<< polycontact >>
|
||||
rect 27 51 31 55
|
||||
rect 10 42 14 46
|
||||
rect 23 44 27 48
|
||||
rect 40 42 44 46
|
||||
rect 12 26 16 30
|
||||
rect 38 26 42 30
|
||||
<< metal1 >>
|
||||
rect 0 72 25 76
|
||||
rect 29 72 54 76
|
||||
rect 0 65 54 69
|
||||
rect 10 46 14 65
|
||||
rect 29 58 33 62
|
||||
rect 17 55 20 58
|
||||
rect 17 51 27 55
|
||||
rect 17 41 20 51
|
||||
rect 34 48 37 58
|
||||
rect 27 44 37 48
|
||||
rect 34 41 37 44
|
||||
rect 40 46 44 65
|
||||
rect 6 35 9 39
|
||||
rect 45 35 48 39
|
||||
rect 25 25 29 29
|
||||
rect 25 13 29 17
|
||||
rect 0 9 25 13
|
||||
rect 29 9 54 13
|
||||
rect 0 2 16 6
|
||||
rect 20 2 34 6
|
||||
rect 38 2 54 6
|
||||
<< m2contact >>
|
||||
rect 25 72 29 76
|
||||
rect 25 58 29 62
|
||||
rect 2 35 6 39
|
||||
rect 16 26 20 30
|
||||
rect 48 35 52 39
|
||||
rect 34 26 38 30
|
||||
rect 9 19 13 23
|
||||
rect 41 19 45 23
|
||||
rect 16 2 20 6
|
||||
rect 34 2 38 6
|
||||
<< metal2 >>
|
||||
rect 2 39 6 76
|
||||
rect 2 0 6 35
|
||||
rect 9 23 13 76
|
||||
rect 25 62 29 72
|
||||
rect 9 0 13 19
|
||||
rect 16 6 20 26
|
||||
rect 34 6 38 26
|
||||
rect 41 23 45 76
|
||||
rect 41 0 45 19
|
||||
rect 48 39 52 76
|
||||
rect 48 0 52 35
|
||||
<< bb >>
|
||||
rect 0 0 54 74
|
||||
<< labels >>
|
||||
rlabel metal1 27 4 27 4 1 wl1
|
||||
rlabel psubstratepcontact 27 11 27 11 1 gnd
|
||||
rlabel metal1 19 67 19 67 1 wl0
|
||||
rlabel metal2 4 7 4 7 2 bl0
|
||||
rlabel metal2 11 7 11 7 1 bl1
|
||||
rlabel metal2 43 7 43 7 1 br1
|
||||
rlabel metal2 50 7 50 7 8 br0
|
||||
rlabel metal1 19 74 19 74 5 vdd
|
||||
<< end >>
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
|
||||
.SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
|
||||
MM9 RA_to_R_right wl1 br1 gnd n w=1.6u l=0.4u
|
||||
MM8 RA_to_R_right Q gnd gnd n w=1.6u l=0.4u
|
||||
MM7 RA_to_R_left vdd gnd gnd n w=1.6u l=0.4u
|
||||
MM6 RA_to_R_left wl1 bl1 gnd n w=1.6u l=0.4u
|
||||
MM5 Q wl0 bl0 gnd n w=1.2u l=0.4u
|
||||
MM4 vdd wl0 br0 gnd n w=1.2u l=0.4u
|
||||
MM1 Q vdd gnd gnd n w=2.4u l=0.4u
|
||||
MM0 vdd Q gnd gnd n w=2.4u l=0.4u
|
||||
MM3 Q vdd vdd vdd p w=0.8u l=0.4u
|
||||
MM2 vdd Q vdd vdd p w=0.8u l=0.4u
|
||||
.ENDS
|
||||
|
||||
Loading…
Reference in New Issue