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Merge branch 'fix_rbl_cell_connections' of https://github.com/VLSIDA/PrivateRAM into fix_rbl_cell_connections

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Matt Guthaus
2018-11-05 13:33:17 -08:00
parent 66225ae21c 0ec16c2b68
commit 35f795d44d
1 changed files with 8 additions and 9 deletions
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technology/freepdk45/sp_lib/replica_cell_6t.sp
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+8 -9
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@@ -1,16 +1,15 @@
.SUBCKT replica_cell_6t bl br wl vdd gnd
* Inverter 1
MM4 Qbar gnd vdd vdd PMOS_VTG W=90n L=50n
MM0 Qbar gnd gnd gnd NMOS_VTG W=205.00n L=50n
MM0 vdd Q gnd gnd NMOS_VTG W=205.00n L=50n
MM4 vdd Q vdd vdd PMOS_VTG W=90n L=50n
* Inverter 2
MM5 gnd Qbar vdd vdd PMOS_VTG W=90n L=50n
MM1 gnd Qbar gnd gnd NMOS_VTG W=205.00n L=50n
* Inverer 2
MM1 Q vdd gnd gnd NMOS_VTG W=205.00n L=50n
MM5 Q vdd vdd vdd PMOS_VTG W=90n L=50n
* Access transistors
MM3 bl wl gnd gnd NMOS_VTG W=135.00n L=50n
MM2 br wl Qbar gnd NMOS_VTG W=135.00n L=50n
.ENDS replica_cell_6t
MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n
MM2 br wl vdd gnd NMOS_VTG W=135.00n L=50n
.ENDS cell_6t