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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

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This commit is contained in:
Michael Timothy Grimes
2018-09-11 17:33:17 -07:00
parent 38a1f35ff0 ac3cc5c79b
commit bfc855b8b1
42 changed files with 1490 additions and 1269 deletions
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compiler/tests/21_hspice_delay_test.py
+17 -16
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@@ -50,28 +50,29 @@ class timing_sram_test(openram_test):
slews = [tech.spice["rise_time"]*2]
data = d.analyze(probe_address, probe_data, slews, loads)
#Assumes single rw port (6t sram)
if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [2.5829000000000004],
'delay_lh': [0.2255964],
golden_data = {'delay_hl0': [2.5829000000000004],
'delay_lh0': [0.2255964],
'leakage_power': 0.0019498999999999996,
'min_period': 4.844,
'read0_power': [0.055371399999999994],
'read1_power': [0.0520225],
'slew_hl': [0.0794261],
'slew_lh': [0.0236264],
'write0_power': [0.06545659999999999],
'write1_power': [0.057846299999999996]}
'read0_power0': [0.055371399999999994],
'read1_power0': [0.0520225],
'slew_hl0': [0.0794261],
'slew_lh0': [0.0236264],
'write0_power0': [0.06545659999999999],
'write1_power0': [0.057846299999999996]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'delay_hl': [4.0249],
'delay_lh': [2.2611],
golden_data = {'delay_hl0': [4.0249],
'delay_lh0': [2.2611],
'leakage_power': 0.0257389,
'min_period': 4.688,
'read0_power': [24.9279],
'read1_power': [24.0219],
'slew_hl': [0.8500753999999999],
'slew_lh': [0.4122653],
'write0_power': [28.197600000000005],
'write1_power': [25.685]}
'read0_power0': [24.9279],
'read1_power0': [24.0219],
'slew_hl0': [0.8500753999999999],
'slew_lh0': [0.4122653],
'write0_power0': [28.197600000000005],
'write1_power0': [25.685]}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
compiler/tests/21_ngspice_delay_test.py
+16 -16
View File
@@ -51,27 +51,27 @@ class timing_sram_test(openram_test):
data = d.analyze(probe_address, probe_data, slews, loads)
if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [2.584251],
'delay_lh': [0.22870469999999998],
golden_data = {'delay_hl0': [2.584251],
'delay_lh0': [0.22870469999999998],
'leakage_power': 0.0009567935,
'min_period': 4.844,
'read0_power': [0.0547588],
'read1_power': [0.051159970000000006],
'slew_hl': [0.08164099999999999],
'slew_lh': [0.025474979999999998],
'write0_power': [0.06513271999999999],
'write1_power': [0.058057000000000004]}
'read0_power0': [0.0547588],
'read1_power0': [0.051159970000000006],
'slew_hl0': [0.08164099999999999],
'slew_lh0': [0.025474979999999998],
'write0_power0': [0.06513271999999999],
'write1_power0': [0.058057000000000004]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'delay_hl': [4.221382999999999],
'delay_lh': [2.6459520000000003],
golden_data = {'delay_hl0': [4.221382999999999],
'delay_lh0': [2.6459520000000003],
'leakage_power': 0.0013865260000000001,
'min_period': 4.688,
'read0_power': [26.699669999999998],
'read1_power': [26.13123],
'slew_hl': [0.9821776000000001],
'slew_lh': [1.5791520000000001],
'write0_power': [30.71939],
'write1_power': [27.44753]}
'read0_power0': [26.699669999999998],
'read1_power0': [26.13123],
'slew_hl0': [0.9821776000000001],
'slew_lh0': [1.5791520000000001],
'write0_power0': [30.71939],
'write1_power0': [27.44753]}
else:
self.assertTrue(False) # other techs fail
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
+4 -37
View File
@@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){
cell_leakage_power : 0;
bus(DIN){
bus_type : DATA;
direction : in;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
direction : input;
capacitance : 0.2091;
memory_write(){
address : ADDR;
clocked_on : clk;
}
}
bus(DOUT){
bus_type : DATA;
direction : out;
direction : output;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
memory_read(){
@@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
+4 -37
View File
@@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){
cell_leakage_power : 0;
bus(DIN){
bus_type : DATA;
direction : in;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
direction : input;
capacitance : 0.2091;
memory_write(){
address : ADDR;
clocked_on : clk;
}
}
bus(DOUT){
bus_type : DATA;
direction : out;
direction : output;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
memory_read(){
@@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
+4 -37
View File
@@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){
cell_leakage_power : 0;
bus(DIN){
bus_type : DATA;
direction : in;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
direction : input;
capacitance : 0.2091;
memory_write(){
address : ADDR;
clocked_on : clk;
}
}
bus(DOUT){
bus_type : DATA;
direction : out;
direction : output;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
memory_read(){
@@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib
+4 -37
View File
@@ -87,16 +87,16 @@ cell (sram_2_16_1_scn3me_subm){
cell_leakage_power : 0;
bus(DIN){
bus_type : DATA;
direction : in;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
direction : input;
capacitance : 9.8242;
memory_write(){
address : ADDR;
clocked_on : clk;
}
}
bus(DOUT){
bus_type : DATA;
direction : out;
direction : output;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
memory_read(){
@@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){
}
}
pin(OEb){
direction : input;
capacitance : 9.8242;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
}
pin(WEb){
direction : input;
capacitance : 9.8242;
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib
+6 -39
View File
@@ -87,20 +87,20 @@ cell (sram_2_16_1_scn3me_subm){
cell_leakage_power : 0;
bus(DIN){
bus_type : DATA;
direction : in;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
direction : input;
capacitance : 9.8242;
memory_write(){
address : ADDR;
address : ADDR0;
clocked_on : clk;
}
}
bus(DOUT){
bus_type : DATA;
direction : out;
direction : output;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
memory_read(){
address : ADDR;
address : ADDR0;
}
pin(DOUT[1:0]){
timing(){
@@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){
}
}
pin(OEb){
direction : input;
capacitance : 9.8242;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(WEb){
direction : input;
capacitance : 9.8242;
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib
+4 -37
View File
@@ -87,16 +87,16 @@ cell (sram_2_16_1_scn3me_subm){
cell_leakage_power : 0;
bus(DIN){
bus_type : DATA;
direction : in;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
direction : input;
capacitance : 9.8242;
memory_write(){
address : ADDR;
clocked_on : clk;
}
}
bus(DOUT){
bus_type : DATA;
direction : out;
direction : output;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
memory_read(){
@@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){
}
}
pin(OEb){
direction : input;
capacitance : 9.8242;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
}
pin(WEb){
direction : input;
capacitance : 9.8242;
compiler/tests/testutils.py
+3
View File
@@ -183,6 +183,9 @@ class openram_test(unittest.TestCase):
# 4. Check if remaining string matches
if line1 != line2:
#Uncomment if you want to see all the individual chars of the two lines
#print(str([i for i in line1]))
#print(str([i for i in line2]))
if mismatches==0:
debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2))
mismatches += 1