diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 3ac5ea63..554d6d36 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -602,6 +602,7 @@ class layout(lef.lef): """ Connect a mapping of pin -> name for a bus. This could be replaced with a channel router in the future. + NOTE: This has only really been tested with point-to-point connections (not multiple pins on a net). """ (horizontal_layer, via_layer, vertical_layer)=layer_stack if horizontal: @@ -711,16 +712,18 @@ class layout(lef.lef): self.add_wire(layer_stack, [pin.center(), mid, trunk_mid]) - def create_channel_route(self, route_map, top_pins, bottom_pins, offset, + def create_channel_route(self, netlist, pins, offset, layer_stack=("metal1", "via1", "metal2"), pitch=None, vertical=False): """ - This is a simple channel route for one-to-one connections that - will jog the top route whenever there is a conflict. It does NOT - try to minimize the number of tracks -- instead, it picks an order to avoid the vertical - conflicts between pins. - """ + The net list is a list of the nets. Each net is a list of pin + names to be connected. Pins is a dictionary of the pin names + to the pin structures. Offset is the lower-left of where the + routing channel will start. This does NOT try to minimize the + number of tracks -- instead, it picks an order to avoid the + vertical conflicts between pins. + """ def remove_net_from_graph(pin, g): # Remove the pin from the keys g.pop(pin,None) @@ -732,11 +735,32 @@ class layout(lef.lef): g[other_pin]=conflicts return g + def vcg_pins_overlap(pins1, pins2, vertical): + # Check all the pin pairs on two nets and return a pin + # overlap if any pin overlaps vertically + for pin1 in pins1: + for pin2 in pins2: + if vcg_pin_overlap(pin1, pin2, vertical): + return True + + return False + + def vcg_pin_overlap(pin1, pin2, vertical): + # Check for vertical overlap of the two pins + + # Pin 1 must be in the "TOP" set + x_overlap = pin1.by() > pin2.by() and abs(pin1.center().x-pin2.center().x)self.word_size or self.probe_data<0: debug.error("Given probe_data is not an integer to specify a data bit",1) + + #Adding port options here which the characterizer cannot handle. Some may be added later like ROM + if len(self.read_ports) == 0: + debug.error("Characterizer does not currently support SRAMs without read ports.",1) + if len(self.write_ports) == 0: + debug.error("Characterizer does not currently support SRAMs without write ports.",1) def write_generic_stimulus(self): """ Create the instance, supplies, loads, and access transistors. """ @@ -74,11 +80,13 @@ class delay(): self.sf.write("\n* Instantiation of the SRAM\n") self.stim.inst_sram(abits=self.addr_size, dbits=self.word_size, + port_info=(self.total_port_num,self.readwrite_port_num,self.read_ports,self.write_ports), sram_name=self.name) self.sf.write("\n* SRAM output loads\n") - for i in range(self.word_size): - self.sf.write("CD{0} DOUT[{0}] 0 {1}f\n".format(i,self.load)) + for port in self.read_ports: + for i in range(self.word_size): + self.sf.write("CD{0}{1} DOUT{0}[{1}] 0 {2}f\n".format(port,i,self.load)) def write_delay_stimulus(self): @@ -137,7 +145,7 @@ class delay(): self.check_arguments() # obtains list of time-points for each rising clk edge - self.create_test_cycles() + #self.create_test_cycles() # creates and opens stimulus file for writing temp_stim = "{0}/stim.sp".format(OPTS.openram_temp) @@ -155,17 +163,21 @@ class delay(): # generate data and addr signals self.sf.write("\n* Generation of data and address signals\n") - for i in range(self.word_size): - self.stim.gen_constant(sig_name="DIN[{0}]".format(i), - v_val=0) - for i in range(self.addr_size): - self.stim.gen_constant(sig_name="A[{0}]".format(i), - v_val=0) + for write_port in self.write_ports: + for i in range(self.word_size): + self.stim.gen_constant(sig_name="DIN{0}[{1}] ".format(write_port, i), + v_val=0) + for port in range(self.total_port_num): + for i in range(self.addr_size): + self.stim.gen_constant(sig_name="A{0}[{1}]".format(port, i), + v_val=0) # generate control signals self.sf.write("\n* Generation of control signals\n") - self.stim.gen_constant(sig_name="CSb", v_val=self.vdd_voltage) - self.stim.gen_constant(sig_name="WEb", v_val=self.vdd_voltage) + for port in range(self.total_port_num): + self.stim.gen_constant(sig_name="CSB{0}".format(port), v_val=self.vdd_voltage) + if port in self.read_ports and port in self.write_ports: + self.stim.gen_constant(sig_name="WEB{0}".format(port), v_val=self.vdd_voltage) self.sf.write("\n* Generation of global clock signal\n") self.stim.gen_constant(sig_name="CLK", v_val=0) @@ -177,90 +189,105 @@ class delay(): self.sf.close() - def write_delay_measures(self): + def write_delay_measures_read_port(self, port): """ - Write the measure statements to quantify the delay and power results. + Write the measure statements to quantify the delay and power results for a read port. """ - self.sf.write("\n* Measure statements for delay and power\n") - - # Output some comments to aid where cycles start and - # what is happening - for comment in self.cycle_comments: - self.sf.write("* {}\n".format(comment)) - # Trigger on the clk of the appropriate cycle trig_name = "clk" - targ_name = "{0}".format("DOUT[{0}]".format(self.probe_data)) + #Target name should be an input to the function or a member variable. That way, the ports can be singled out for testing + targ_name = "{0}".format("DOUT{0}[{1}]".format(port,self.probe_data)) trig_val = targ_val = 0.5 * self.vdd_voltage # Delay the target to measure after the negative edge - self.stim.gen_meas_delay(meas_name="DELAY_HL", + self.stim.gen_meas_delay(meas_name="DELAY_HL{0}".format(port), trig_name=trig_name, targ_name=targ_name, trig_val=trig_val, targ_val=targ_val, trig_dir="RISE", targ_dir="FALL", - trig_td=self.cycle_times[self.read0_cycle], - targ_td=self.cycle_times[self.read0_cycle]) + trig_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]], + targ_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]) - self.stim.gen_meas_delay(meas_name="DELAY_LH", + self.stim.gen_meas_delay(meas_name="DELAY_LH{0}".format(port), trig_name=trig_name, targ_name=targ_name, trig_val=trig_val, targ_val=targ_val, trig_dir="RISE", targ_dir="RISE", - trig_td=self.cycle_times[self.read1_cycle], - targ_td=self.cycle_times[self.read1_cycle]) + trig_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]], + targ_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]) - self.stim.gen_meas_delay(meas_name="SLEW_HL", + self.stim.gen_meas_delay(meas_name="SLEW_HL{0}".format(port), trig_name=targ_name, targ_name=targ_name, trig_val=0.9*self.vdd_voltage, targ_val=0.1*self.vdd_voltage, trig_dir="FALL", targ_dir="FALL", - trig_td=self.cycle_times[self.read0_cycle], - targ_td=self.cycle_times[self.read0_cycle]) + trig_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]], + targ_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]) - self.stim.gen_meas_delay(meas_name="SLEW_LH", + self.stim.gen_meas_delay(meas_name="SLEW_LH{0}".format(port), trig_name=targ_name, targ_name=targ_name, trig_val=0.1*self.vdd_voltage, targ_val=0.9*self.vdd_voltage, trig_dir="RISE", targ_dir="RISE", - trig_td=self.cycle_times[self.read1_cycle], - targ_td=self.cycle_times[self.read1_cycle]) + trig_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]], + targ_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]) # add measure statements for power - t_initial = self.cycle_times[self.write0_cycle] - t_final = self.cycle_times[self.write0_cycle+1] - self.stim.gen_meas_power(meas_name="WRITE0_POWER", + t_initial = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]] + t_final = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]+1] + self.stim.gen_meas_power(meas_name="READ0_POWER{0}".format(port), t_initial=t_initial, t_final=t_final) - t_initial = self.cycle_times[self.write1_cycle] - t_final = self.cycle_times[self.write1_cycle+1] - self.stim.gen_meas_power(meas_name="WRITE1_POWER", + t_initial = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]] + t_final = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]+1] + self.stim.gen_meas_power(meas_name="READ1_POWER{0}".format(port), t_initial=t_initial, t_final=t_final) - t_initial = self.cycle_times[self.read0_cycle] - t_final = self.cycle_times[self.read0_cycle+1] - self.stim.gen_meas_power(meas_name="READ0_POWER", + def write_delay_measures_write_port(self, port): + """ + Write the measure statements to quantify the power results for a write port. + """ + # add measure statements for power + t_initial = self.cycle_times[self.measure_cycles["write0_{0}".format(port)]] + t_final = self.cycle_times[self.measure_cycles["write0_{0}".format(port)]+1] + self.stim.gen_meas_power(meas_name="WRITE0_POWER{0}".format(port), t_initial=t_initial, t_final=t_final) - t_initial = self.cycle_times[self.read1_cycle] - t_final = self.cycle_times[self.read1_cycle+1] - self.stim.gen_meas_power(meas_name="READ1_POWER", + t_initial = self.cycle_times[self.measure_cycles["write1_{0}".format(port)]] + t_final = self.cycle_times[self.measure_cycles["write1_{0}".format(port)]+1] + self.stim.gen_meas_power(meas_name="WRITE1_POWER{0}".format(port), t_initial=t_initial, t_final=t_final) + def write_delay_measures(self): + """ + Write the measure statements to quantify the delay and power results for all targeted ports. + """ + self.sf.write("\n* Measure statements for delay and power\n") + + # Output some comments to aid where cycles start and + # what is happening + for comment in self.cycle_comments: + self.sf.write("* {}\n".format(comment)) + + for read_port in self.targ_read_ports: + self.write_delay_measures_read_port(read_port) + for write_port in self.targ_write_ports: + self.write_delay_measures_write_port(write_port) + def write_power_measures(self): """ Write the measure statements to quantify the leakage power only. @@ -275,7 +302,7 @@ class delay(): t_initial=t_initial, t_final=t_final) - def find_feasible_period(self): + def find_feasible_period_one_port(self, port): """ Uses an initial period and finds a feasible period before we run the binary search algorithm to find min period. We check if @@ -283,34 +310,98 @@ class delay(): double the period until we find a valid period to use as a starting point. """ - + debug.check(port in self.read_ports, "Characterizer requires a read port to determine a period.") + #Adding this as a sanity check for editing this function later. This function assumes period has been set previously + debug.check(self.period > 0, "Initial starting period not defined") feasible_period = float(tech.spice["feasible_period"]) - time_out = 8 + #feasible_period = float(2.5)#What happens if feasible starting point is wrong? + time_out = 9 while True: - debug.info(1, "Trying feasible period: {0}ns".format(feasible_period)) time_out -= 1 - if (time_out <= 0): debug.error("Timed out, could not find a feasible period.",2) + + #Clear any write target ports and set read port + self.targ_write_ports = [] + self.targ_read_ports = [port] + success = False + + debug.info(1, "Trying feasible period: {0}ns on Port {1}".format(feasible_period, port)) self.period = feasible_period (success, results)=self.run_delay_simulation() + #Clear these target ports after simulation + self.targ_read_ports = [] + if not success: feasible_period = 2 * feasible_period - continue - feasible_delay_lh = results["delay_lh"] - feasible_slew_lh = results["slew_lh"] - feasible_delay_hl = results["delay_hl"] - feasible_slew_hl = results["slew_hl"] + break + feasible_delay_lh = results["delay_lh{0}".format(port)] + feasible_delay_hl = results["delay_hl{0}".format(port)] + feasible_slew_lh = results["slew_lh{0}".format(port)] + feasible_slew_hl = results["slew_hl{0}".format(port)] delay_str = "feasible_delay {0:.4f}ns/{1:.4f}ns".format(feasible_delay_lh, feasible_delay_hl) slew_str = "slew {0:.4f}ns/{1:.4f}ns".format(feasible_slew_lh, feasible_slew_hl) - debug.info(1, "Found feasible_period: {0}ns {1} {2} ".format(feasible_period, + debug.info(2, "feasible_period passed for Port {3}: {0}ns {1} {2} ".format(feasible_period, delay_str, - slew_str)) - self.period = feasible_period - return (feasible_delay_lh, feasible_delay_hl) - + slew_str, + port)) + #Add feasible delays of port to dict + #feasible_delays_lh[port] = feasible_delay_lh + #feasible_delays_hl[port] = feasible_delay_hl + + if success: + debug.info(1, "Found feasible_period: {0}ns".format(feasible_period)) + self.period = feasible_period + return (feasible_delay_lh, feasible_delay_hl) + def find_feasible_period(self): + """ + Loops through all read ports determining the feasible period and collecting + delay information from each port. + """ + feasible_delays_lh = {} + feasible_delays_hl = {} + self.period = float(tech.spice["feasible_period"]) + + #Get initial feasible period from first port + (feasible_delays_lh[0], feasible_delays_hl[0]) = self.find_feasible_period_one_port(self.read_ports[0]) + previous_period = self.period + + + #Loops through all the ports checks if the feasible period works. Everything restarts it if does not. + #Write ports do not produce delays which is why they are not included here. + i = 1 + while i < len(self.read_ports): + port = self.read_ports[i] + (feasible_delays_lh[port], feasible_delays_hl[port]) = self.find_feasible_period_one_port(port) + #Function sets the period. Restart the entire process if period changes to collect accurate delays + if self.period > previous_period: + i = 0 + else: + i+=1 + previous_period = self.period + return (feasible_delays_lh, feasible_delays_hl) + + + def parse_values(self, values_names, mult = 1.0): + """Parse multiple values in the timing output file. Optional multiplier.""" + values = [] + all_values_floats = True + for vname in values_names: + #ngspice converts all measure characters to lowercase, not tested on other sims + value = parse_spice_list("timing", vname.lower()) + #Check if any of the values fail to parse + if type(value)!=float: + all_values_floats = False + values.append(value) + + #Apply Multiplier only if all values are floats. Let other check functions handle this error. + if all_values_floats: + return {values_names[i]:values[i]*mult for i in range(len(values))} + else: + return {values_names[i]:values[i] for i in range(len(values))} + def run_delay_simulation(self): """ This tries to simulate a period and checks if the result works. If @@ -318,37 +409,38 @@ class delay(): works on the trimmed netlist by default, so powers do not include leakage of all cells. """ - + result = {} # Checking from not data_value to data_value self.write_delay_stimulus() self.stim.run_sim() - delay_hl = parse_spice_list("timing", "delay_hl") - delay_lh = parse_spice_list("timing", "delay_lh") - slew_hl = parse_spice_list("timing", "slew_hl") - slew_lh = parse_spice_list("timing", "slew_lh") - delays = (delay_hl, delay_lh, slew_hl, slew_lh) - - read0_power=parse_spice_list("timing", "read0_power") - write0_power=parse_spice_list("timing", "write0_power") - read1_power=parse_spice_list("timing", "read1_power") - write1_power=parse_spice_list("timing", "write1_power") - - if not self.check_valid_delays(delays): - return (False,{}) + + #Loop through all targeted ports and collect delays and powers. + #Too much duplicate code here. Try reducing + for port in self.targ_read_ports: + delay_names = ["delay_hl{0}".format(port), "delay_lh{0}".format(port), + "slew_hl{0}".format(port), "slew_lh{0}".format(port)] + delays = self.parse_values(delay_names, 1e9) # scale delays to ns + if not self.check_valid_delays((delays[delay_names[0]],delays[delay_names[1]],delays[delay_names[2]],delays[delay_names[3]])): + return (False,{}) + result.update(delays) - # For debug, you sometimes want to inspect each simulation. - #key=raw_input("press return to continue") - - # Scale results to ns and mw, respectively - result = { "delay_hl" : delay_hl*1e9, - "delay_lh" : delay_lh*1e9, - "slew_hl" : slew_hl*1e9, - "slew_lh" : slew_lh*1e9, - "read0_power" : read0_power*1e3, - "read1_power" : read1_power*1e3, - "write0_power" : write0_power*1e3, - "write1_power" : write1_power*1e3} + power_names = ["read0_power{0}".format(port), "read1_power{0}".format(port)] + powers = self.parse_values(power_names, 1e3) # scale power to mw + #Check that power parsing worked. + for name, power in powers.items(): + if type(power)!=float: + debug.error("Failed to Parse Power Values:\n\t\t{0}".format(powers),1) #Printing the entire dict looks bad. + result.update(powers) + + for port in self.targ_write_ports: + power_names = ["write0_power{0}".format(port), "write1_power{0}".format(port)] + powers = self.parse_values(power_names, 1e3) # scale power to mw + #Check that power parsing worked. + for name, power in powers.items(): + if type(power)!=float: + debug.error("Failed to Parse Power Values:\n\t\t{0}".format(powers),1) #Printing the entire dict looks bad. + result.update(powers) # The delay is from the negative edge for our SRAM return (True,result) @@ -359,18 +451,21 @@ class delay(): This simulates a disabled SRAM to get the leakage power when it is off. """ - + debug.info(1, "Performing leakage power simulations.") self.write_power_stimulus(trim=False) self.stim.run_sim() leakage_power=parse_spice_list("timing", "leakage_power") debug.check(leakage_power!="Failed","Could not measure leakage power.") - + debug.info(1, "Leakage power of full array is {0} mW".format(leakage_power*1e3)) + #debug + #sys.exit(1) self.write_power_stimulus(trim=True) self.stim.run_sim() trim_leakage_power=parse_spice_list("timing", "leakage_power") debug.check(trim_leakage_power!="Failed","Could not measure leakage power.") - + debug.info(1, "Leakage power of trimmed array is {0} mW".format(trim_leakage_power*1e3)) + # For debug, you sometimes want to inspect each simulation. #key=raw_input("press return to continue") return (leakage_power*1e3, trim_leakage_power*1e3) @@ -389,11 +484,7 @@ class delay(): delays_str, slews_str)) return False - # Scale delays to ns (they previously could have not been floats) - delay_hl *= 1e9 - delay_lh *= 1e9 - slew_hl *= 1e9 - slew_lh *= 1e9 + delays_str = "delay_hl={0} delay_lh={1}".format(delay_hl, delay_lh) slews_str = "slew_hl={0} slew_lh={1}".format(slew_hl,slew_lh) if delay_hl>self.period or delay_lh>self.period or slew_hl>self.period or slew_lh>self.period: @@ -408,87 +499,102 @@ class delay(): return True + def find_min_period(self, feasible_delays_lh, feasible_delays_hl): + """ + Determine the minimum period for all ports. + """ - def find_min_period(self, feasible_delay_lh, feasible_delay_hl): + feasible_period = ub_period = self.period + lb_period = 0.0 + target_period = 0.5 * (ub_period + lb_period) + + #Find the minimum period for all ports. Start at one port and perform binary search then use that delay as a starting position. + #For testing purposes, only checks read ports. + for port in self.read_ports: + target_period = self.find_min_period_one_port(feasible_delays_lh, feasible_delays_hl, port, lb_period, ub_period, target_period) + #The min period of one port becomes the new lower bound. Reset the upper_bound. + lb_period = target_period + ub_period = feasible_period + + #Clear the target ports before leaving + self.targ_read_ports = [] + self.targ_write_ports = [] + return target_period + + def find_min_period_one_port(self, feasible_delays_lh, feasible_delays_hl, port, lb_period, ub_period, target_period): """ Searches for the smallest period with output delays being within 5% of - long period. + long period. For the current logic to characterize multiport, bound are required as an input. """ - previous_period = ub_period = self.period - lb_period = 0.0 - - # Binary search algorithm to find the min period (max frequency) of design + #previous_period = ub_period = self.period + #ub_period = self.period + #lb_period = 0.0 + #target_period = 0.5 * (ub_period + lb_period) + + # Binary search algorithm to find the min period (max frequency) of input port time_out = 25 + self.targ_read_ports = [port] while True: time_out -= 1 if (time_out <= 0): debug.error("Timed out, could not converge on minimum period.",2) - target_period = 0.5 * (ub_period + lb_period) self.period = target_period - debug.info(1, "MinPeriod Search: {0}ns (ub: {1} lb: {2})".format(target_period, + debug.info(1, "MinPeriod Search Port {3}: {0}ns (ub: {1} lb: {2})".format(target_period, ub_period, - lb_period)) + lb_period, + port)) - if self.try_period(feasible_delay_lh, feasible_delay_hl): + if self.try_period(feasible_delays_lh, feasible_delays_hl): ub_period = target_period else: lb_period = target_period if relative_compare(ub_period, lb_period, error_tolerance=0.05): - # ub_period is always feasible + # ub_period is always feasible. When done with a port, set the target period of the next port as the lower bound + # and reset the upperbound return ub_period + #target_period = lb_period = ub_period + #ub_period = previous_period + #break + + #Update target + target_period = 0.5 * (ub_period + lb_period) - - def try_period(self, feasible_delay_lh, feasible_delay_hl): + + def try_period(self, feasible_delays_lh, feasible_delays_hl): """ This tries to simulate a period and checks if the result works. If it does and the delay is within 5% still, it returns True. """ + # Run Delay simulation but Power results not used. + (success, results) = self.run_delay_simulation() + if not success: + return False + + #Check the values of target readwrite and read ports. Write ports do not produce delays in this current version + for port in self.targ_read_ports: + delay_hl = results["delay_hl{0}".format(port)] + delay_lh = results["delay_lh{0}".format(port)] + slew_hl = results["slew_hl{0}".format(port)] + slew_lh = results["slew_lh{0}".format(port)] - # Checking from not data_value to data_value - self.write_delay_stimulus() - self.stim.run_sim() - delay_hl = parse_spice_list("timing", "delay_hl") - delay_lh = parse_spice_list("timing", "delay_lh") - slew_hl = parse_spice_list("timing", "slew_hl") - slew_lh = parse_spice_list("timing", "slew_lh") - # if it failed or the read was longer than a period - if type(delay_hl)!=float or type(delay_lh)!=float or type(slew_lh)!=float or type(slew_hl)!=float: - debug.info(2,"Invalid measures: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period, - delay_hl, - delay_lh, - slew_hl, - slew_lh)) - return False - delay_hl *= 1e9 - delay_lh *= 1e9 - slew_hl *= 1e9 - slew_lh *= 1e9 - if delay_hl>self.period or delay_lh>self.period or slew_hl>self.period or slew_lh>self.period: - debug.info(2,"Too long delay/slew: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period, - delay_hl, - delay_lh, - slew_hl, - slew_lh)) - return False - else: - if not relative_compare(delay_lh,feasible_delay_lh,error_tolerance=0.05): - debug.info(2,"Delay too big {0} vs {1}".format(delay_lh,feasible_delay_lh)) + if not relative_compare(delay_lh,feasible_delays_lh[port],error_tolerance=0.05): + debug.info(2,"Delay too big {0} vs {1}".format(delay_lh,feasible_delays_lh[port])) return False - elif not relative_compare(delay_hl,feasible_delay_hl,error_tolerance=0.05): - debug.info(2,"Delay too big {0} vs {1}".format(delay_hl,feasible_delay_hl)) + elif not relative_compare(delay_hl,feasible_delays_hl[port],error_tolerance=0.05): + debug.info(2,"Delay too big {0} vs {1}".format(delay_hl,feasible_delays_hl[port])) return False + #key=raw_input("press return to continue") - #key=raw_input("press return to continue") - - debug.info(2,"Successful period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period, - delay_hl, - delay_lh, - slew_hl, - slew_lh)) + debug.info(2,"Successful period {0}, Port {5}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period, + delay_hl, + delay_lh, + slew_hl, + slew_lh, + port)) return True def set_probe(self,probe_address, probe_data): @@ -527,11 +633,14 @@ class delay(): """ Main function to characterize an SRAM for a table. Computes both delay and power characterization. """ - # Data structure for all the characterization values - char_data = {} - self.set_probe(probe_address, probe_data) - + + self.create_port_names() + + self.create_char_data_dict() + + self.load=max(loads) + self.slew=max(slews) # This is for debugging a full simulation # debug.info(0,"Debug simulation running...") # target_period=50.0 @@ -542,31 +651,49 @@ class delay(): # self.try_period(target_period, feasible_delay_lh, feasible_delay_hl) # sys.exit(1) - + #For debugging, skips characterization and returns dummy values. + # char_data = self.char_data + # i = 1.0 + # for slew in slews: + # for load in loads: + # for k,v in char_data.items(): + # char_data[k].append(i) + # i+=1.0 + # char_data["min_period"] = i + # char_data["leakage_power"] = i+1.0 + # return char_data + # 1) Find a feasible period and it's corresponding delays using the trimmed array. - self.load=max(loads) - self.slew=max(slews) - (feasible_delay_lh, feasible_delay_hl) = self.find_feasible_period() - debug.check(feasible_delay_lh>0,"Negative delay may not be possible") - debug.check(feasible_delay_hl>0,"Negative delay may not be possible") + (feasible_delays_lh, feasible_delays_hl) = self.find_feasible_period() + #Check all the delays + for k,v in feasible_delays_lh.items(): + debug.check(v>0,"Negative delay may not be possible") + for k,v in feasible_delays_hl.items(): + debug.check(v>0,"Negative delay may not be possible") + # 2) Finds the minimum period without degrading the delays by X% self.set_load_slew(max(loads),max(slews)) - min_period = self.find_min_period(feasible_delay_lh, feasible_delay_hl) + min_period = self.find_min_period(feasible_delays_lh, feasible_delays_hl) debug.check(type(min_period)==float,"Couldn't find minimum period.") - debug.info(1, "Min Period: {0}n with a delay of {1} / {2}".format(min_period, feasible_delay_lh, feasible_delay_hl)) - char_data["min_period"] = round_time(min_period) - - # Make a list for each type of measurement to append results to - for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power", - "read1_power", "write0_power", "write1_power", "leakage_power"]: - char_data[m]=[] + debug.info(1, "Min Period Found: {0}ns".format(min_period)) + self.char_data["min_period"] = round_time(min_period) # 3) Find the leakage power of the trimmmed and UNtrimmed arrays. (full_array_leakage, trim_array_leakage)=self.run_power_simulation() - char_data["leakage_power"]=full_array_leakage - + self.char_data["leakage_power"]=full_array_leakage + leakage_offset = full_array_leakage - trim_array_leakage + # 4) At the minimum period, measure the delay, slew and power for all slew/load pairs. + self.simulate_loads_and_slews(slews, loads, leakage_offset) + + return self.char_data + + def simulate_loads_and_slews(self, slews, loads, leakage_offset): + """Simulate all specified output loads and input slews pairs""" + #Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways. + self.targ_read_ports = self.read_ports + self.targ_write_ports = self.write_ports for slew in slews: for load in loads: self.set_load_slew(load,slew) @@ -576,109 +703,123 @@ class delay(): for k,v in delay_results.items(): if "power" in k: # Subtract partial array leakage and add full array leakage for the power measures - char_data[k].append(v - trim_array_leakage + full_array_leakage) + self.char_data[k].append(v + leakage_offset) else: - char_data[k].append(v) - - - - return char_data - - - - def add_data(self, data): + self.char_data[k].append(v) + + def add_data(self, data, port): """ Add the array of data values """ debug.check(len(data)==self.word_size, "Invalid data word size.") + debug.check(port < len(self.data_values), "Port number cannot index data values.") index = 0 for c in data: if c=="0": - self.data_values[index].append(0) + self.data_values[port][index].append(0) elif c=="1": - self.data_values[index].append(1) + self.data_values[port][index].append(1) else: debug.error("Non-binary data string",1) index += 1 - def add_address(self, address): + def add_address(self, address, port): """ Add the array of address values """ debug.check(len(address)==self.addr_size, "Invalid address size.") index = 0 for c in address: if c=="0": - self.addr_values[index].append(0) + self.addr_values[port][index].append(0) elif c=="1": - self.addr_values[index].append(1) + self.addr_values[port][index].append(1) else: debug.error("Non-binary address string",1) index += 1 - def add_noop(self, comment, address, data): - """ Add the control values for a read cycle. """ - self.cycle_comments.append("Cycle {0:2d}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_times), + def add_noop_one_port(self, address, data, port): + """ Add the control values for a noop to a single port. """ + #This is to be used as a helper function for the other add functions. Cycle and comments are omitted. + self.add_control_one_port(port, "noop") + if port in self.write_ports: + self.add_data(data,port) + self.add_address(address, port) + + def add_noop_all_ports(self, comment, address, data): + """ Add the control values for a noop to all ports. """ + self.cycle_comments.append("Cycle {0:2d}\tPort All\t{1:5.2f}ns:\t{2}".format(len(self.cycle_times), self.t_current, comment)) self.cycle_times.append(self.t_current) self.t_current += self.period - self.web_values.append(1) - self.csb_values.append(1) - - self.add_data(data) - self.add_address(address) + + for port in range(self.total_port_num): + self.add_noop_one_port(address, data, port) - def add_read(self, comment, address, data): + def add_read(self, comment, address, data, port): """ Add the control values for a read cycle. """ - self.cycle_comments.append("Cycle {0:2d}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments), + debug.check(port in self.read_ports, "Cannot add read cycle to a write port.") + self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments), self.t_current, - comment)) + comment, + port)) + self.cycle_times.append(self.t_current) + self.t_current += self.period + self.add_control_one_port(port, "read") + + #If the port is also a readwrite then add data. + if port in self.write_ports: + self.add_data(data,port) + self.add_address(address, port) + + #This value is hard coded here. Possibly change to member variable or set in add_noop_one_port + noop_data = "0"*self.word_size + #Add noops to all other ports. + for unselected_port in range(self.total_port_num): + if unselected_port != port: + self.add_noop_one_port(address, noop_data, unselected_port) + + def add_write(self, comment, address, data, port): + """ Add the control values for a write cycle. """ + debug.check(port in self.write_ports, "Cannot add read cycle to a read port.") + self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments), + self.t_current, + comment, + port)) self.cycle_times.append(self.t_current) self.t_current += self.period - self.web_values.append(1) - self.csb_values.append(0) - - self.add_data(data) - self.add_address(address) + self.add_control_one_port(port, "write") + self.add_data(data,port) + self.add_address(address,port) + #This value is hard coded here. Possibly change to member variable or set in add_noop_one_port + noop_data = "0"*self.word_size + #Add noops to all other ports. + for unselected_port in range(self.total_port_num): + if unselected_port != port: + self.add_noop_one_port(address, noop_data, unselected_port) + + def add_control_one_port(self, port, op): + """Appends control signals for operation to a given port""" + #Determine values to write to port + web_val = 1 + csb_val = 1 + if op == "read": + csb_val = 0 + elif op == "write": + csb_val = 0 + web_val = 0 + elif op != "noop": + debug.error("Could not add control signals for port {0}. Command {1} not recognized".format(port,op),1) + #Append the values depending on the type of port + self.csb_values[port].append(csb_val) + #If port is in both lists, add rw control signal. Condition indicates its a RW port. + if port < len(self.web_values): + self.web_values[port].append(web_val) - def add_write(self, comment, address, data): - """ Add the control values for a read cycle. """ - self.cycle_comments.append("Cycle {0:2d}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments), - self.t_current, - comment)) - self.cycle_times.append(self.t_current) - self.t_current += self.period - - self.web_values.append(0) - self.csb_values.append(0) - - self.add_data(data) - self.add_address(address) - - def create_test_cycles(self): - """Returns a list of key time-points [ns] of the waveform (each rising edge) - of the cycles to do a timing evaluation. The last time is the end of the simulation - and does not need a rising edge.""" - - # Start at time 0 - self.t_current = 0 - - # Cycle times (positive edge) with comment - self.cycle_comments = [] - self.cycle_times = [] - - # Control logic signals each cycle - self.web_values = [] - self.csb_values = [] - - # Address and data values for each address/data bit - self.data_values=[] - for i in range(self.word_size): - self.data_values.append([]) - self.addr_values=[] - for i in range(self.addr_size): - self.addr_values.append([]) + def gen_test_cycles_one_port(self, read_port, write_port): + """Intended but not implemented: Returns a list of key time-points [ns] of the waveform (each rising edge) + of the cycles to do a timing evaluation of a single port. Current: Values overwritten for multiple calls""" # Create the inverse address for a scratch address inverse_address = "" @@ -694,51 +835,119 @@ class delay(): data_ones = "1"*self.word_size data_zeros = "0"*self.word_size - self.add_noop("Idle cycle (no positive clock edge)", + if self.t_current == 0: + self.add_noop_all_ports("Idle cycle (no positive clock edge)", inverse_address, data_zeros) - + self.add_write("W data 1 address 0..00", - inverse_address,data_ones) + inverse_address,data_ones,write_port) self.add_write("W data 0 address 11..11 to write value", - self.probe_address,data_zeros) - self.write0_cycle=len(self.cycle_times)-1 # Remember for power measure + self.probe_address,data_zeros,write_port) + self.measure_cycles["write0_{0}".format(write_port)] = len(self.cycle_times)-1 + #self.write0_cycle=len(self.cycle_times)-1 # Remember for power measure # This also ensures we will have a H->L transition on the next read self.add_read("R data 1 address 00..00 to set DOUT caps", - inverse_address,data_zeros) + inverse_address,data_zeros,read_port) self.add_read("R data 0 address 11..11 to check W0 worked", - self.probe_address,data_zeros) - self.read0_cycle=len(self.cycle_times)-1 # Remember for power measure + self.probe_address,data_zeros,read_port) + self.measure_cycles["read0_{0}".format(read_port)] = len(self.cycle_times)-1 + #self.read0_cycle=len(self.cycle_times)-1 # Remember for power measure - self.add_noop("Idle cycle (if read takes >1 cycle)", + self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)", inverse_address,data_zeros) - self.idle_cycle=len(self.cycle_times)-1 # Remember for power measure + #Does not seem like is is used anywhere commenting out for now. + #self.idle_cycle=len(self.cycle_times)-1 # Remember for power measure self.add_write("W data 1 address 11..11 to write value", - self.probe_address,data_ones) - self.write1_cycle=len(self.cycle_times)-1 # Remember for power measure + self.probe_address,data_ones,write_port) + self.measure_cycles["write1_{0}".format(write_port)] = len(self.cycle_times)-1 + #self.write1_cycle=len(self.cycle_times)-1 # Remember for power measure self.add_write("W data 0 address 00..00 to clear DIN caps", - inverse_address,data_zeros) + inverse_address,data_zeros,write_port) # This also ensures we will have a L->H transition on the next read self.add_read("R data 0 address 00..00 to clear DOUT caps", - inverse_address,data_zeros) + inverse_address,data_zeros,read_port) self.add_read("R data 1 address 11..11 to check W1 worked", + self.probe_address,data_zeros,read_port) + self.measure_cycles["read1_{0}".format(read_port)] = len(self.cycle_times)-1 + #self.read1_cycle=len(self.cycle_times)-1 # Remember for power measure + + self.add_noop_all_ports("Idle cycle (if read takes >1 cycle))", self.probe_address,data_zeros) - self.read1_cycle=len(self.cycle_times)-1 # Remember for power measure - - self.add_noop("Idle cycle (if read takes >1 cycle))", - self.probe_address,data_zeros) + + def get_available_port(self,get_read_port): + """Returns the first accessible read or write port. """ + if get_read_port and len(self.read_ports) > 0: + return self.read_ports[0] + elif not get_read_port and len(self.write_ports) > 0: + return self.write_ports[0] + return None + + def create_test_cycles(self): + """Returns a list of key time-points [ns] of the waveform (each rising edge) + of the cycles to do a timing evaluation. The last time is the end of the simulation + and does not need a rising edge.""" + #Using this requires setting at least one port to target for simulation. + if len(self.targ_write_ports) == 0 and len(self.targ_read_ports) == 0: + debug.error("No ports selected for characterization.",1) + + # Start at time 0 + self.t_current = 0 + # Cycle times (positive edge) with comment + self.cycle_comments = [] + self.cycle_times = [] + self.measure_cycles = {} + # Control signals for ports. These are not the final signals and will likely be changed later. + #write enable bar for readwrite ports to control read or write + self.web_values = [[] for i in range(self.readwrite_port_num)] + #csb represents a basic "enable" signal that all ports have. + self.csb_values = [[] for i in range(self.total_port_num)] + + # Address and data values for each address/data bit. A dict of 3d lists of size #ports x bits x cycles. + self.data_values=[[[] for i in range(self.addr_size)]]*len(self.write_ports) + self.addr_values=[[[] for i in range(self.addr_size)]]*self.total_port_num + + #Get any available read/write port in case only a single write or read ports is being characterized. + cur_read_port = self.get_available_port(get_read_port=True) + cur_write_port = self.get_available_port(get_read_port=False) + + #These checks should be superceded by check_arguments which should have been called earlier, so this is a double check. + debug.check(cur_read_port != None, "Characterizer requires at least 1 read port") + debug.check(cur_write_port != None, "Characterizer requires at least 1 write port") + + #Characterizing the remaining target ports. Not the final design. + write_pos = 0 + read_pos = 0 + while True: + #Exit when all ports have been characterized + if write_pos >= len(self.targ_write_ports) and read_pos >= len(self.targ_read_ports): + break + + #Select new write and/or read ports for the next cycle. Use previous port if none remaining. + if write_pos < len(self.targ_write_ports): + cur_write_port = self.targ_write_ports[write_pos] + write_pos+=1 + if read_pos < len(self.targ_read_ports): + cur_read_port = self.targ_read_ports[read_pos] + read_pos+=1 + + #Add test cycle of read/write port pair. One port could have been used already, but the other has not. + self.gen_test_cycles_one_port(cur_read_port, cur_write_port) def analytical_delay(self,sram, slews, loads): - """ Just return the analytical model results for the SRAM. + """ Return the analytical model results for the SRAM. """ + debug.check(OPTS.num_rw_ports < 2 and OPTS.num_w_ports < 1 and OPTS.num_r_ports < 1 , + "Analytical characterization does not currently support multiport.") + delay_lh = [] delay_hl = [] slew_lh = [] @@ -761,35 +970,72 @@ class delay(): debug.info(1,"Leakage Power: {0} mW".format(power.leakage)) data = {"min_period": 0, - "delay_lh": delay_lh, - "delay_hl": delay_hl, - "slew_lh": slew_lh, - "slew_hl": slew_hl, - "read0_power": power.dynamic, - "read1_power": power.dynamic, - "write0_power": power.dynamic, - "write1_power": power.dynamic, + "delay_lh0": delay_lh, + "delay_hl0": delay_hl, + "slew_lh0": slew_lh, + "slew_hl0": slew_hl, + "read0_power0": power.dynamic, + "read1_power0": power.dynamic, + "write0_power0": power.dynamic, + "write1_power0": power.dynamic, "leakage_power": power.leakage } return data def gen_data(self): """ Generates the PWL data inputs for a simulation timing test. """ - for i in range(self.word_size): - sig_name="DIN[{0}]".format(i) - self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[i], self.period, self.slew, 0.05) + for write_port in self.write_ports: + for i in range(self.word_size): + sig_name="DIN{0}[{1}] ".format(write_port, i) + self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[write_port][i], self.period, self.slew, 0.05) def gen_addr(self): """ Generates the address inputs for a simulation timing test. This alternates between all 1's and all 0's for the address. """ - for i in range(self.addr_size): - sig_name = "A[{0}]".format(i) - self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[i], self.period, self.slew, 0.05) - + for port in range(self.total_port_num): + for i in range(self.addr_size): + sig_name = "A{0}[{1}]".format(port,i) + self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[port][i], self.period, self.slew, 0.05) def gen_control(self): """ Generates the control signals """ - self.stim.gen_pwl("csb", self.cycle_times, self.csb_values, self.period, self.slew, 0.05) - self.stim.gen_pwl("web", self.cycle_times, self.web_values, self.period, self.slew, 0.05) + for port in range(self.total_port_num): + self.stim.gen_pwl("CSB{0}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05) + + for readwrite_port in range(self.readwrite_port_num): + self.stim.gen_pwl("WEB{0}".format(readwrite_port), self.cycle_times, self.web_values[readwrite_port], self.period, self.slew, 0.05) + + + def create_port_names(self): + """Generates the port names to be used in characterization and sets default simulation target ports""" + self.write_ports = [] + self.read_ports = [] + self.total_port_num = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports + + #save a member variable to avoid accessing global. readwrite ports have different control signals. + self.readwrite_port_num = OPTS.num_rw_ports + + #Generate the port names. readwrite ports are required to be added first for this to work. + for readwrite_port_num in range(OPTS.num_rw_ports): + self.read_ports.append(readwrite_port_num) + self.write_ports.append(readwrite_port_num) + #This placement is intentional. It makes indexing input data easier. See self.data_values + for write_port_num in range(OPTS.num_rw_ports, OPTS.num_rw_ports+OPTS.num_w_ports): + self.write_ports.append(write_port_num) + for read_port_num in range(OPTS.num_rw_ports+OPTS.num_w_ports, OPTS.num_rw_ports+OPTS.num_w_ports+OPTS.num_r_ports): + self.read_ports.append(read_port_num) + + #Set the default target ports for simulation. Default is all the ports. + self.targ_read_ports = self.read_ports + self.targ_write_ports = self.write_ports + + def create_char_data_dict(self): + """Make a dict of lists for each type of measurement to append results to""" + #Making this a member variable may not be the best option, but helps reduce code clutter + self.char_data = {} + for port in range(self.total_port_num): + for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power", + "read1_power", "write0_power", "write1_power"]: + self.char_data ["{0}{1}".format(m,port)]=[] \ No newline at end of file diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 2ac65513..9f04fd7f 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -12,18 +12,43 @@ class lib: """ lib file generation.""" def __init__(self, out_dir, sram, sp_file, use_model=OPTS.analytical_delay): + #Temporary Workaround to here to set num of ports. Crashes if set in config file. + #OPTS.num_rw_ports = 2 + #OPTS.num_r_ports = 1 + #OPTS.num_w_ports = 1 + self.out_dir = out_dir self.sram = sram self.sp_file = sp_file self.use_model = use_model - + self.gen_port_names() #copy and paste from delay.py, names are not final will likely be changed later. + self.prepare_tables() self.create_corners() self.characterize_corners() - + def gen_port_names(self): + """Generates the port names to be written to the lib file""" + #This is basically a copy and paste of whats in delay.py as well. Something more efficient should be done here. + self.write_ports = [] + self.read_ports = [] + self.total_port_num = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports + + #save a member variable to avoid accessing global. readwrite ports have different control signals. + self.readwrite_port_num = OPTS.num_rw_ports + + #Generate the port names. readwrite ports are required to be added first for this to work. + for readwrite_port_num in range(OPTS.num_rw_ports): + self.read_ports.append(readwrite_port_num) + self.write_ports.append(readwrite_port_num) + #This placement is intentional. It makes indexing input data easier. See self.data_values + for read_port_num in range(OPTS.num_rw_ports, OPTS.num_r_ports): + self.read_ports.append(read_port_num) + for write_port_num in range(OPTS.num_rw_ports+OPTS.num_r_ports, OPTS.num_w_ports): + self.write_ports.append(write_port_num) + def prepare_tables(self): """ Determine the load/slews if they aren't specified in the config file. """ # These are the parameters to determine the table sizes @@ -85,13 +110,14 @@ class lib: self.write_header() - self.write_data_bus() - - self.write_addr_bus() - - self.write_control_pins() - - self.write_clk() + #Loop over all readwrite ports. This is debugging. Will change later. + for port in range(self.total_port_num): + #set the read and write port as inputs. + self.write_data_bus(port) + self.write_addr_bus(port) + self.write_control_pins(port) #need to split this into sram and port control signals + + self.write_clk_timing_power() self.write_footer() @@ -127,9 +153,14 @@ class lib: self.lib.write(" dont_touch : true;\n") self.lib.write(" area : {};\n\n".format(self.sram.width * self.sram.height)) + #Build string of all control signals. This is subject to change once control signals finalized. + control_str = 'CSb0' #assume at least 1 port + for i in range(1, self.total_port_num): + control_str += ' & CSb{0}'.format(i) + # Leakage is included in dynamic when macro is enabled self.lib.write(" leakage_power () {\n") - self.lib.write(" when : \"CSb\";\n") + self.lib.write(" when : \"{0}\";\n".format(control_str)) self.lib.write(" value : {};\n".format(self.char_results["leakage_power"])) self.lib.write(" }\n") self.lib.write(" cell_leakage_power : {};\n".format(0)) @@ -295,65 +326,72 @@ class lib: self.lib.write(" }\n") self.lib.write(" }\n") - - - def write_data_bus(self): + def write_data_bus_output(self, read_port): """ Adds data bus timing results.""" - self.lib.write(" bus(DIN){\n") + self.lib.write(" bus(DOUT{0}){{\n".format(read_port)) self.lib.write(" bus_type : DATA; \n") - self.lib.write(" direction : in; \n") - # This is conservative, but limit to range that we characterized. - self.lib.write(" max_capacitance : {0}; \n".format(max(self.loads))) - self.lib.write(" min_capacitance : {0}; \n".format(min(self.loads))) - self.lib.write(" memory_write(){ \n") - self.lib.write(" address : ADDR; \n") - self.lib.write(" clocked_on : clk; \n") - self.lib.write(" }\n") - - self.lib.write(" bus(DOUT){\n") - self.lib.write(" bus_type : DATA; \n") - self.lib.write(" direction : out; \n") + self.lib.write(" direction : output; \n") # This is conservative, but limit to range that we characterized. self.lib.write(" max_capacitance : {0}; \n".format(max(self.loads))) self.lib.write(" min_capacitance : {0}; \n".format(min(self.loads))) self.lib.write(" memory_read(){ \n") - self.lib.write(" address : ADDR; \n") + self.lib.write(" address : ADDR{0}; \n".format(read_port)) self.lib.write(" }\n") - self.lib.write(" pin(DOUT[{0}:0]){{\n".format(self.sram.word_size - 1)) + self.lib.write(" pin(DOUT{1}[{0}:0]){{\n".format(self.sram.word_size - 1, read_port)) self.write_FF_setuphold() self.lib.write(" timing(){ \n") self.lib.write(" timing_sense : non_unate; \n") self.lib.write(" related_pin : \"clk\"; \n") self.lib.write(" timing_type : rising_edge; \n") self.lib.write(" cell_rise(CELL_TABLE) {\n") - self.write_values(self.char_results["delay_lh"],len(self.loads)," ") + self.write_values(self.char_results["delay_lh{0}".format(read_port)],len(self.loads)," ") self.lib.write(" }\n") # rise delay self.lib.write(" cell_fall(CELL_TABLE) {\n") - self.write_values(self.char_results["delay_hl"],len(self.loads)," ") + self.write_values(self.char_results["delay_hl{0}".format(read_port)],len(self.loads)," ") self.lib.write(" }\n") # fall delay self.lib.write(" rise_transition(CELL_TABLE) {\n") - self.write_values(self.char_results["slew_lh"],len(self.loads)," ") + self.write_values(self.char_results["slew_lh{0}".format(read_port)],len(self.loads)," ") self.lib.write(" }\n") # rise trans self.lib.write(" fall_transition(CELL_TABLE) {\n") - self.write_values(self.char_results["slew_hl"],len(self.loads)," ") + self.write_values(self.char_results["slew_hl{0}".format(read_port)],len(self.loads)," ") self.lib.write(" }\n") # fall trans self.lib.write(" }\n") # timing self.lib.write(" }\n") # pin self.lib.write(" }\n\n") # bus + def write_data_bus_input(self, write_port): + """ Adds data bus timing results.""" - def write_addr_bus(self): + self.lib.write(" bus(DIN{0}){{\n".format(write_port)) + self.lib.write(" bus_type : DATA; \n") + self.lib.write(" direction : input; \n") + # This is conservative, but limit to range that we characterized. + self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"])) + self.lib.write(" memory_write(){ \n") + self.lib.write(" address : ADDR{0}; \n".format(write_port)) + self.lib.write(" clocked_on : clk; \n") + self.lib.write(" }\n") + self.lib.write(" }\n") + + def write_data_bus(self, port): + """ Adds data bus timing results.""" + if port in self.write_ports: + self.write_data_bus_input(port) + if port in self.read_ports: + self.write_data_bus_output(port) + + def write_addr_bus(self, port): """ Adds addr bus timing results.""" - - self.lib.write(" bus(ADDR){\n") + + self.lib.write(" bus(ADDR{0}){{\n".format(port)) self.lib.write(" bus_type : ADDR; \n") self.lib.write(" direction : input; \n") self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"])) self.lib.write(" max_transition : {0};\n".format(self.slews[-1])) - self.lib.write(" pin(ADDR[{0}:0])".format(self.sram.addr_size - 1)) + self.lib.write(" pin(ADDR{1}[{0}:0])".format(self.sram.addr_size - 1, port)) self.lib.write("{\n") self.write_FF_setuphold() @@ -361,10 +399,13 @@ class lib: self.lib.write(" }\n\n") - def write_control_pins(self): + def write_control_pins(self, port): """ Adds control pins timing results.""" - - ctrl_pin_names = ["CSb", "OEb", "WEb"] + #The control pins are still to be determined. This is a placeholder for what could be. + ctrl_pin_names = ["CSb{0}".format(port)] + if port in self.write_ports and port in self.read_ports: + ctrl_pin_names.append("WEb{0}".format(port)) + for i in ctrl_pin_names: self.lib.write(" pin({0})".format(i)) self.lib.write("{\n") @@ -373,8 +414,7 @@ class lib: self.write_FF_setuphold() self.lib.write(" }\n\n") - - def write_clk(self): + def write_clk_timing_power(self): """ Adds clk pin timing results.""" self.lib.write(" pin(clk){\n") @@ -383,41 +423,10 @@ class lib: # FIXME: This depends on the clock buffer size in the control logic self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"])) - # Find the average power of 1 and 0 bits for writes and reads over all loads/slews - # Could make it a table, but this is fine for now. - avg_write_power = np.mean(self.char_results["write1_power"] + self.char_results["write0_power"]) - avg_read_power = np.mean(self.char_results["read1_power"] + self.char_results["read0_power"]) - - # Equally divide read/write power between first and second half of clock period - self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"!CSb & clk & !WEb\"; \n") - self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) - self.lib.write(" }\n") - self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) - self.lib.write(" }\n") - self.lib.write(" }\n") - - self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"!CSb & !clk & WEb\"; \n") - self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) - self.lib.write(" }\n") - self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) - self.lib.write(" }\n") - self.lib.write(" }\n") - # Have 0 internal power when disabled, this will be represented as leakage power. - self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"CSb\"; \n") - self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"0\");\n") - self.lib.write(" }\n") - self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"0\");\n") - self.lib.write(" }\n") - self.lib.write(" }\n") + #Add power values for the ports. lib generated with this is not syntactically correct. TODO once + #top level is done. + for port in range(self.total_port_num): + self.add_clk_control_power(port) min_pulse_width = round_time(self.char_results["min_period"])/2.0 min_period = round_time(self.char_results["min_period"]) @@ -443,7 +452,51 @@ class lib: self.lib.write(" }\n") self.lib.write(" }\n") self.lib.write(" }\n") + + def add_clk_control_power(self, port): + """Writes powers under the clock pin group for a specified port""" + #Web added to read/write ports. Likely to change when control logic finished. + web_name = "" + + if port in self.write_ports: + if port in self.read_ports: + web_name = " & !WEb{0}".format(port) + avg_write_power = np.mean(self.char_results["write1_power{0}".format(port)] + self.char_results["write0_power{0}".format(port)]) + self.lib.write(" internal_power(){\n") + self.lib.write(" when : \"!CSb{0} & clk{1}\"; \n".format(port, web_name)) + self.lib.write(" rise_power(scalar){\n") + self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) + self.lib.write(" }\n") + self.lib.write(" fall_power(scalar){\n") + self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) + self.lib.write(" }\n") + self.lib.write(" }\n") + if port in self.read_ports: + if port in self.write_ports: + web_name = " & WEb{0}".format(port) + avg_read_power = np.mean(self.char_results["read1_power{0}".format(port)] + self.char_results["read0_power{0}".format(port)]) + self.lib.write(" internal_power(){\n") + self.lib.write(" when : \"!CSb{0} & !clk{1}\"; \n".format(port, web_name)) + self.lib.write(" rise_power(scalar){\n") + self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) + self.lib.write(" }\n") + self.lib.write(" fall_power(scalar){\n") + self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) + self.lib.write(" }\n") + self.lib.write(" }\n") + + # Have 0 internal power when disabled, this will be represented as leakage power. + self.lib.write(" internal_power(){\n") + self.lib.write(" when : \"CSb{0}\"; \n".format(port)) + self.lib.write(" rise_power(scalar){\n") + self.lib.write(" values(\"0\");\n") + self.lib.write(" }\n") + self.lib.write(" fall_power(scalar){\n") + self.lib.write(" values(\"0\");\n") + self.lib.write(" }\n") + self.lib.write(" }\n") + def compute_delay(self): """ Do the analysis if we haven't characterized the SRAM yet """ if not hasattr(self,"d"): diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index aaeff0cd..ee35af46 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -276,17 +276,36 @@ class setup_hold(): HL_setup = [] LH_hold = [] HL_hold = [] + + #For debugging, skips characterization and returns dummy values. + # i = 1.0 + # for self.related_input_slew in related_slews: + # for self.constrained_input_slew in constrained_slews: + # LH_setup.append(i) + # HL_setup.append(i+1.0) + # LH_hold.append(i+2.0) + # HL_hold.append(i+3.0) + # i+=4.0 + + # times = {"setup_times_LH": LH_setup, + # "setup_times_HL": HL_setup, + # "hold_times_LH": LH_hold, + # "hold_times_HL": HL_hold + # } + # return times + + for self.related_input_slew in related_slews: for self.constrained_input_slew in constrained_slews: debug.info(1, "Clock slew: {0} Data slew: {1}".format(self.related_input_slew,self.constrained_input_slew)) LH_setup_time = self.setup_LH_time() - debug.info(1, " Setup Time for low_to_high transistion: {0}".format(LH_setup_time)) + debug.info(1, " Setup Time for low_to_high transition: {0}".format(LH_setup_time)) HL_setup_time = self.setup_HL_time() - debug.info(1, " Setup Time for high_to_low transistion: {0}".format(HL_setup_time)) + debug.info(1, " Setup Time for high_to_low transition: {0}".format(HL_setup_time)) LH_hold_time = self.hold_LH_time() - debug.info(1, " Hold Time for low_to_high transistion: {0}".format(LH_hold_time)) + debug.info(1, " Hold Time for low_to_high transition: {0}".format(LH_hold_time)) HL_hold_time = self.hold_HL_time() - debug.info(1, " Hold Time for high_to_low transistion: {0}".format(HL_hold_time)) + debug.info(1, " Hold Time for high_to_low transition: {0}".format(HL_hold_time)) LH_setup.append(LH_setup_time) HL_setup.append(HL_setup_time) LH_hold.append(LH_hold_time) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 2cca1384..b99aadd4 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -30,18 +30,33 @@ class stimuli(): self.device_models = tech.spice["fet_models"][self.process] - def inst_sram(self, abits, dbits, sram_name): + def inst_sram(self, abits, dbits, port_info, sram_name): """ Function to instatiate an SRAM subckt. """ self.sf.write("Xsram ") - for i in range(dbits): - self.sf.write("DIN[{0}] ".format(i)) - for i in range(abits): - self.sf.write("A[{0}] ".format(i)) - for i in tech.spice["control_signals"]: - self.sf.write("{0} ".format(i)) + + #Un-tuple the port names. This was done to avoid passing them all as arguments. Could be improved still. + #This should be generated from the pin list of the sram... change when multiport pins done. + (total_port_num,readwrite_num,read_ports,write_ports) = port_info + + for write_input in write_ports: + for i in range(dbits): + self.sf.write("DIN{0}[{1}] ".format(write_input, i)) + + for port in range(total_port_num): + for i in range(abits): + self.sf.write("A{0}[{1}] ".format(port,i)) + + #These control signals assume 6t sram i.e. a single readwrite port. If multiple readwrite ports are used then add more + #control signals. Not sure if this is correct, consider a temporary change until control signals for multiport are finalized. + for port in range(total_port_num): + self.sf.write("CSB{0} ".format(port)) + for readwrite_port in range(readwrite_num): + self.sf.write("WEB{0} ".format(readwrite_port)) + self.sf.write("{0} ".format(tech.spice["clk"])) - for i in range(dbits): - self.sf.write("DOUT[{0}] ".format(i)) + for read_output in read_ports: + for i in range(dbits): + self.sf.write("DOUT{0}[{1}] ".format(read_output, i)) self.sf.write("{0} {1} ".format(self.vdd_name, self.gnd_name)) self.sf.write("{0}\n".format(sram_name)) diff --git a/compiler/example_config_freepdk45.py b/compiler/example_config_freepdk45.py index 774d41fb..32655f09 100644 --- a/compiler/example_config_freepdk45.py +++ b/compiler/example_config_freepdk45.py @@ -10,3 +10,10 @@ temperatures = [25] output_path = "temp" output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name) +#Below are some additions to test additional ports on sram +#bitcell = "pbitcell" + +# These are the configuration parameters +#rw_ports = 2 +#r_ports = 2 +#w_ports = 2 diff --git a/compiler/example_config_scn3me_subm.py b/compiler/example_config_scn3me_subm.py index 356b4542..fec65d95 100644 --- a/compiler/example_config_scn3me_subm.py +++ b/compiler/example_config_scn3me_subm.py @@ -9,4 +9,3 @@ temperatures = [ 25 ] output_path = "temp" output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name) - diff --git a/compiler/modules/ms_flop.py b/compiler/modules/ms_flop.py index e04b4246..bb8e2ca2 100644 --- a/compiler/modules/ms_flop.py +++ b/compiler/modules/ms_flop.py @@ -43,8 +43,8 @@ class ms_flop(design.design): from tech import spice, parameter c_load = load c_para = spice["flop_para_cap"]#ff - transistion_prob = spice["flop_transisition_prob"] - return transistion_prob*(c_load + c_para) + transition_prob = spice["flop_transition_prob"] + return transition_prob*(c_load + c_para) \ No newline at end of file diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index e39f95bc..8b3d1716 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -279,5 +279,5 @@ class pinv(pgate.pgate): """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - transistion_prob = spice["inv_transisition_prob"] - return transistion_prob*(c_load + c_para) + transition_prob = spice["inv_transition_prob"] + return transition_prob*(c_load + c_para) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index d38c7de4..14923a84 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -240,5 +240,5 @@ class pnand2(pgate.pgate): """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - transistion_prob = spice["nand2_transisition_prob"] - return transistion_prob*(c_load + c_para) + transition_prob = spice["nand2_transition_prob"] + return transition_prob*(c_load + c_para) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index b4e11b32..75887ed3 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -259,5 +259,5 @@ class pnand3(pgate.pgate): """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - transistion_prob = spice["nand3_transisition_prob"] - return transistion_prob*(c_load + c_para) + transition_prob = spice["nand3_transition_prob"] + return transition_prob*(c_load + c_para) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 8f7dcea4..87196342 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -237,6 +237,6 @@ class pnor2(pgate.pgate): """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - transistion_prob = spice["nor2_transisition_prob"] - return transistion_prob*(c_load + c_para) + transition_prob = spice["nor2_transition_prob"] + return transition_prob*(c_load + c_para) diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index 0f625e15..1eaa6abb 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -321,8 +321,10 @@ class sram_1bank(sram_base): route_map = list(zip(bank_names, dff_names)) dff_pins = {key: self.data_dff_inst.get_pin(key) for key in dff_names } - bank_pins = {key: self.bank_inst.get_pin(key) for key in bank_names } - self.create_horizontal_channel_route(route_map, dff_pins, bank_pins, offset) + bank_pins = {key: self.bank_inst.get_pin(key) for key in bank_names } + # Combine the dff and bank pins into a single dictionary of pin name to pin. + all_pins = {**dff_pins, **bank_pins} + self.create_horizontal_channel_route(route_map, all_pins, offset) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 93fc8413..74db4757 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -50,28 +50,29 @@ class timing_sram_test(openram_test): slews = [tech.spice["rise_time"]*2] data = d.analyze(probe_address, probe_data, slews, loads) + #Assumes single rw port (6t sram) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.5829000000000004], - 'delay_lh': [0.2255964], + golden_data = {'delay_hl0': [2.5829000000000004], + 'delay_lh0': [0.2255964], 'leakage_power': 0.0019498999999999996, 'min_period': 4.844, - 'read0_power': [0.055371399999999994], - 'read1_power': [0.0520225], - 'slew_hl': [0.0794261], - 'slew_lh': [0.0236264], - 'write0_power': [0.06545659999999999], - 'write1_power': [0.057846299999999996]} + 'read0_power0': [0.055371399999999994], + 'read1_power0': [0.0520225], + 'slew_hl0': [0.0794261], + 'slew_lh0': [0.0236264], + 'write0_power0': [0.06545659999999999], + 'write1_power0': [0.057846299999999996]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'delay_hl': [4.0249], - 'delay_lh': [2.2611], + golden_data = {'delay_hl0': [4.0249], + 'delay_lh0': [2.2611], 'leakage_power': 0.0257389, 'min_period': 4.688, - 'read0_power': [24.9279], - 'read1_power': [24.0219], - 'slew_hl': [0.8500753999999999], - 'slew_lh': [0.4122653], - 'write0_power': [28.197600000000005], - 'write1_power': [25.685]} + 'read0_power0': [24.9279], + 'read1_power0': [24.0219], + 'slew_hl0': [0.8500753999999999], + 'slew_lh0': [0.4122653], + 'write0_power0': [28.197600000000005], + 'write1_power0': [25.685]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index d54cdf54..ca873339 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -51,27 +51,27 @@ class timing_sram_test(openram_test): data = d.analyze(probe_address, probe_data, slews, loads) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.584251], - 'delay_lh': [0.22870469999999998], + golden_data = {'delay_hl0': [2.584251], + 'delay_lh0': [0.22870469999999998], 'leakage_power': 0.0009567935, 'min_period': 4.844, - 'read0_power': [0.0547588], - 'read1_power': [0.051159970000000006], - 'slew_hl': [0.08164099999999999], - 'slew_lh': [0.025474979999999998], - 'write0_power': [0.06513271999999999], - 'write1_power': [0.058057000000000004]} + 'read0_power0': [0.0547588], + 'read1_power0': [0.051159970000000006], + 'slew_hl0': [0.08164099999999999], + 'slew_lh0': [0.025474979999999998], + 'write0_power0': [0.06513271999999999], + 'write1_power0': [0.058057000000000004]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'delay_hl': [4.221382999999999], - 'delay_lh': [2.6459520000000003], + golden_data = {'delay_hl0': [4.221382999999999], + 'delay_lh0': [2.6459520000000003], 'leakage_power': 0.0013865260000000001, 'min_period': 4.688, - 'read0_power': [26.699669999999998], - 'read1_power': [26.13123], - 'slew_hl': [0.9821776000000001], - 'slew_lh': [1.5791520000000001], - 'write0_power': [30.71939], - 'write1_power': [27.44753]} + 'read0_power0': [26.699669999999998], + 'read1_power0': [26.13123], + 'slew_hl0': [0.9821776000000001], + 'slew_lh0': [1.5791520000000001], + 'write0_power0': [30.71939], + 'write1_power0': [27.44753]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index cf9df15f..84f301f8 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + direction : input; + capacitance : 0.2091; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 1.6728; min_capacitance : 0.052275; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){ } } - pin(OEb){ - direction : input; - capacitance : 0.2091; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.015, 0.027",\ - "0.009, 0.015, 0.027",\ - "0.009, 0.015, 0.027"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016"); - } - } - } - pin(WEb){ direction : input; capacitance : 0.2091; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index c14afc35..2fbbd8b8 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + direction : input; + capacitance : 0.2091; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 1.6728; min_capacitance : 0.052275; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){ } } - pin(OEb){ - direction : input; - capacitance : 0.2091; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - } - } - pin(WEb){ direction : input; capacitance : 0.2091; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index 1cd10b44..a3ec121c 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + direction : input; + capacitance : 0.2091; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 1.6728; min_capacitance : 0.052275; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){ } } - pin(OEb){ - direction : input; - capacitance : 0.2091; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.015, 0.027",\ - "0.009, 0.015, 0.027",\ - "0.009, 0.015, 0.027"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016"); - } - } - } - pin(WEb){ direction : input; capacitance : 0.2091; diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib index f43c12c7..e6aa54f9 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_scn3me_subm){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 78.5936; - min_capacitance : 2.45605; + direction : input; + capacitance : 9.8242; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 78.5936; min_capacitance : 2.45605; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){ } } - pin(OEb){ - direction : input; - capacitance : 9.8242; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.076, 0.076, 0.149",\ - "0.076, 0.076, 0.149",\ - "0.076, 0.076, 0.149"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.033, 0.039, 0.027",\ - "0.033, 0.039, 0.027",\ - "0.033, 0.039, 0.027"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, 0.009",\ - "-0.004, -0.004, 0.009",\ - "-0.004, -0.004, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.059, -0.132",\ - "-0.052, -0.059, -0.132",\ - "-0.052, -0.059, -0.132"); - } - } - } - pin(WEb){ direction : input; capacitance : 9.8242; diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib index 6e6c9501..8d774ce5 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib @@ -87,20 +87,20 @@ cell (sram_2_16_1_scn3me_subm){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 78.5936; - min_capacitance : 2.45605; + direction : input; + capacitance : 9.8242; memory_write(){ - address : ADDR; + address : ADDR0; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 78.5936; min_capacitance : 2.45605; memory_read(){ - address : ADDR; + address : ADDR0; } pin(DOUT[1:0]){ timing(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){ } } - pin(OEb){ - direction : input; - capacitance : 9.8242; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - } - } - pin(WEb){ direction : input; capacitance : 9.8242; diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib index 39924746..b514a858 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_scn3me_subm){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 78.5936; - min_capacitance : 2.45605; + direction : input; + capacitance : 9.8242; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 78.5936; min_capacitance : 2.45605; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){ } } - pin(OEb){ - direction : input; - capacitance : 9.8242; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.076, 0.076, 0.149",\ - "0.076, 0.076, 0.149",\ - "0.076, 0.076, 0.149"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.033, 0.039, 0.027",\ - "0.033, 0.039, 0.027",\ - "0.033, 0.039, 0.027"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, 0.009",\ - "-0.004, -0.004, 0.009",\ - "-0.004, -0.004, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.059, -0.132",\ - "-0.052, -0.059, -0.132",\ - "-0.052, -0.059, -0.132"); - } - } - } - pin(WEb){ direction : input; capacitance : 9.8242; diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 64c1c2b4..e1c02f45 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -183,6 +183,9 @@ class openram_test(unittest.TestCase): # 4. Check if remaining string matches if line1 != line2: + #Uncomment if you want to see all the individual chars of the two lines + #print(str([i for i in line1])) + #print(str([i for i in line2])) if mismatches==0: debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2)) mismatches += 1 diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index 91c52a90..1f0ffaab 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -30,7 +30,7 @@ if OPTS.check_lvsdrc and OPTS.tech_name == "freepdk45": debug.check(OPTS.drc_exe[0]!="magic","Magic does not support FreePDK45 for DRC.") if OPTS.drc_exe == None: - pass + from .none import run_drc,print_drc_stats elif "calibre"==OPTS.drc_exe[0]: from .calibre import run_drc,print_drc_stats elif "assura"==OPTS.drc_exe[0]: @@ -41,7 +41,7 @@ else: debug.warning("Did not find a supported DRC tool.") if OPTS.lvs_exe == None: - pass + from .none import run_lvs,print_lvs_stats elif "calibre"==OPTS.lvs_exe[0]: from .calibre import run_lvs,print_lvs_stats elif "assura"==OPTS.lvs_exe[0]: @@ -53,7 +53,7 @@ else: if OPTS.pex_exe == None: - pass + from .none import run_pex,print_pex_stats elif "calibre"==OPTS.pex_exe[0]: from .calibre import run_pex,print_pex_stats elif "magic"==OPTS.pex_exe[0]: diff --git a/compiler/verify/none.py b/compiler/verify/none.py new file mode 100644 index 00000000..531a394d --- /dev/null +++ b/compiler/verify/none.py @@ -0,0 +1,41 @@ +""" +This is a DRC/LVS/PEX interface file the case with no DRC/LVS tools. + +""" +import debug + +# Only print the warning once. +drc_warned = False +lvs_warned = False +pex_warned = False + +def run_drc(cell_name, gds_name, extract=False): + global drc_warned + if not drc_warned: + debug.warning("DRC unable to run.") + drc_warned=True + # Since we warned, return a failing test. + return 1 + +def run_lvs(cell_name, gds_name, sp_name, final_verification=False): + global lvs_warned + if not lvs_warned: + debug.warning("LVS unable to run.") + lvs_warned=True + # Since we warned, return a failing test. + return 1 + +def run_pex(name, gds_name, sp_name, output=None): + global pex_warned + if not pex_warned: + debug.warning("PEX unable to run.") + pex_warned=True + # Since we warned, return a failing test. + return 1 + +def print_drc_stats(): + pass +def print_lvs_stats(): + pass +def print_pex_stats(): + pass diff --git a/lib/freepdk45/sram_1rw_128b_1024w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_128b_1024w_1bank_freepdk45.log index bb655056..e9c97e12 100644 --- a/lib/freepdk45/sram_1rw_128b_1024w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_128b_1024w_1bank_freepdk45.log @@ -84,50 +84,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 5.78125ns (ub: 5.9375 lb: 5.625) [characterizer.delay/analyze]: Min Period: 5.9375n with a delay of 3.1226964 / 0.30308602 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 16788.8 seconds GDS: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.gds ** GDS: 9.0 seconds diff --git a/lib/freepdk45/sram_1rw_128b_1024w_4bank_freepdk45.log b/lib/freepdk45/sram_1rw_128b_1024w_4bank_freepdk45.log index b758b31b..f1c4136a 100644 --- a/lib/freepdk45/sram_1rw_128b_1024w_4bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_128b_1024w_4bank_freepdk45.log @@ -85,50 +85,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 1.953125ns (ub: 2.03125 lb: 1.875) [characterizer.delay/analyze]: Min Period: 2.03125n with a delay of 0.19175762 / 0.17403244 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 35039.9 seconds GDS: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.gds ** GDS: 5.3 seconds diff --git a/lib/freepdk45/sram_1rw_32b_1024w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_32b_1024w_1bank_freepdk45.log index c777cf84..98ec0b81 100644 --- a/lib/freepdk45/sram_1rw_32b_1024w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_32b_1024w_1bank_freepdk45.log @@ -83,50 +83,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125) [characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1713644 / 0.19182711 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 8034.5 seconds GDS: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.gds ** GDS: 3.3 seconds diff --git a/lib/freepdk45/sram_1rw_32b_2048w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_32b_2048w_1bank_freepdk45.log index 7fbf2e95..92673b20 100644 --- a/lib/freepdk45/sram_1rw_32b_2048w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_32b_2048w_1bank_freepdk45.log @@ -83,50 +83,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 2.265625ns (ub: 2.34375 lb: 2.1875) [characterizer.delay/analyze]: Min Period: 2.34375n with a delay of 1.2374402 / 0.25744693 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 12972.2 seconds GDS: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.gds ** GDS: 5.6 seconds diff --git a/lib/freepdk45/sram_1rw_32b_256w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_32b_256w_1bank_freepdk45.log index 27fa6d1d..f7645bc4 100644 --- a/lib/freepdk45/sram_1rw_32b_256w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_32b_256w_1bank_freepdk45.log @@ -83,50 +83,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125) [characterizer.delay/analyze]: Min Period: 2.109375n with a delay of 1.1300259 / 0.13801474 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 4457.6 seconds GDS: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.gds ** GDS: 1.4 seconds diff --git a/lib/freepdk45/sram_1rw_32b_512w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_32b_512w_1bank_freepdk45.log index 310ab3e7..fbb51477 100644 --- a/lib/freepdk45/sram_1rw_32b_512w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_32b_512w_1bank_freepdk45.log @@ -83,50 +83,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125) [characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1419594 / 0.15656674 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 5101.6 seconds GDS: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.gds ** GDS: 1.8 seconds diff --git a/lib/freepdk45/sram_1rw_64b_1024w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_64b_1024w_1bank_freepdk45.log index e1c8fa89..5ec76a8a 100644 --- a/lib/freepdk45/sram_1rw_64b_1024w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_64b_1024w_1bank_freepdk45.log @@ -82,50 +82,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 3.59375ns (ub: 3.75 lb: 3.4375) [characterizer.delay/analyze]: Min Period: 3.59375n with a delay of 1.850756 / 0.23319319 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 9948.6 seconds GDS: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.gds ** GDS: 5.9 seconds diff --git a/lib/freepdk45/sram_1rw_8b_256w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_8b_256w_1bank_freepdk45.log index c3816c2f..a9338950 100644 --- a/lib/freepdk45/sram_1rw_8b_256w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_8b_256w_1bank_freepdk45.log @@ -84,50 +84,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 1.0546875ns (ub: 1.09375 lb: 1.015625) [characterizer.delay/analyze]: Min Period: 1.0546875n with a delay of 0.56986783 / 0.10418749 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 3369.3 seconds GDS: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.gds ** GDS: 0.8 seconds diff --git a/lib/scn3me_subm/sram_1rw_128b_1024w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_128b_1024w_1bank_scn3me_subm.log index f9ec88b7..e228495d 100644 --- a/lib/scn3me_subm/sram_1rw_128b_1024w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_128b_1024w_1bank_scn3me_subm.log @@ -86,50 +86,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 57.5ns (ub: 60.0 lb: 55.0) [characterizer.delay/analyze]: Min Period: 60.0n with a delay of 31.821678 / 3.9657764 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 13865.7 seconds GDS: Writing to ./sram_1rw_128b_1024w_1bank_scn3me_subm.gds ** GDS: 9.5 seconds diff --git a/lib/scn3me_subm/sram_1rw_128b_1024w_2bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_128b_1024w_2bank_scn3me_subm.log index 5f272478..aa01ded4 100644 --- a/lib/scn3me_subm/sram_1rw_128b_1024w_2bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_128b_1024w_2bank_scn3me_subm.log @@ -86,50 +86,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 16.875ns (ub: 17.5 lb: 16.25) [characterizer.delay/analyze]: Min Period: 17.5n with a delay of 9.657173 / 2.0055267 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 19670.7 seconds GDS: Writing to ./sram_1rw_128b_1024w_2bank_scn3me_subm.gds ** GDS: 7.8 seconds diff --git a/lib/scn3me_subm/sram_1rw_128b_1024w_4bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_128b_1024w_4bank_scn3me_subm.log index e7c734c8..4832f9c6 100644 --- a/lib/scn3me_subm/sram_1rw_128b_1024w_4bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_128b_1024w_4bank_scn3me_subm.log @@ -86,50 +86,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 18.125ns (ub: 18.75 lb: 17.5) [characterizer.delay/analyze]: Min Period: 18.75n with a delay of 10.525582 / 2.331161 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 24789.5 seconds GDS: Writing to ./sram_1rw_128b_1024w_4bank_scn3me_subm.gds ** GDS: 4.3 seconds diff --git a/lib/scn3me_subm/sram_1rw_32b_2048w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_32b_2048w_1bank_scn3me_subm.log index 5391de33..8744d09e 100644 --- a/lib/scn3me_subm/sram_1rw_32b_2048w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_32b_2048w_1bank_scn3me_subm.log @@ -84,50 +84,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 16.875ns (ub: 17.5 lb: 16.25) [characterizer.delay/analyze]: Min Period: 16.875n with a delay of 9.1997828 / 3.104732 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 10830.5 seconds GDS: Writing to ./sram_1rw_32b_2048w_1bank_scn3me_subm.gds ** GDS: 5.3 seconds diff --git a/lib/scn3me_subm/sram_1rw_32b_256w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_32b_256w_1bank_scn3me_subm.log index 1ac5ebdd..f361c779 100644 --- a/lib/scn3me_subm/sram_1rw_32b_256w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_32b_256w_1bank_scn3me_subm.log @@ -84,50 +84,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 19.375ns (ub: 20.0 lb: 18.75) [characterizer.delay/analyze]: Min Period: 20.0n with a delay of 10.777462 / 1.9428786 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 3663.3 seconds GDS: Writing to ./sram_1rw_32b_256w_1bank_scn3me_subm.gds ** GDS: 1.2 seconds diff --git a/lib/scn3me_subm/sram_1rw_32b_512w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_32b_512w_1bank_scn3me_subm.log index c74dead5..61ce1268 100644 --- a/lib/scn3me_subm/sram_1rw_32b_512w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_32b_512w_1bank_scn3me_subm.log @@ -84,50 +84,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 19.375ns (ub: 20.0 lb: 18.75) [characterizer.delay/analyze]: Min Period: 20.0n with a delay of 11.057892 / 2.1338514 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 4702.5 seconds GDS: Writing to ./sram_1rw_32b_512w_1bank_scn3me_subm.gds ** GDS: 2.1 seconds diff --git a/lib/scn3me_subm/sram_1rw_64b_1024w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_64b_1024w_1bank_scn3me_subm.log index 82344ea5..1c71e1d6 100644 --- a/lib/scn3me_subm/sram_1rw_64b_1024w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_64b_1024w_1bank_scn3me_subm.log @@ -85,50 +85,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 33.75ns (ub: 35.0 lb: 32.5) [characterizer.delay/analyze]: Min Period: 33.75n with a delay of 18.100242 / 3.0216206 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 9134.8 seconds GDS: Writing to ./sram_1rw_64b_1024w_1bank_scn3me_subm.gds ** GDS: 5.1 seconds diff --git a/lib/scn3me_subm/sram_1rw_8b_256w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_8b_256w_1bank_scn3me_subm.log index 9b31bdda..91425053 100644 --- a/lib/scn3me_subm/sram_1rw_8b_256w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_8b_256w_1bank_scn3me_subm.log @@ -83,50 +83,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 9.0625ns (ub: 9.375 lb: 8.75) [characterizer.delay/analyze]: Min Period: 9.0625n with a delay of 5.0024145 / 1.5312283 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 2269.5 seconds GDS: Writing to ./sram_1rw_8b_256w_1bank_scn3me_subm.gds ** GDS: 0.6 seconds diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 3c28fab5..74bef19c 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -298,11 +298,11 @@ spice["msflop_leakage"] = 1 # Leakage power of flop in nW spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF spice["default_event_rate"] = 100 # Default event activity of every gate. MHz -spice["flop_transisition_prob"] = .5 # Transition probability of inverter. -spice["inv_transisition_prob"] = .5 # Transition probability of inverter. -spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand. -spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand. -spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor. +spice["flop_transition_prob"] = .5 # Transition probability of inverter. +spice["inv_transition_prob"] = .5 # Transition probability of inverter. +spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand. +spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. +spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. ################################################### ##END Spice Simulation Parameters diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index a3f51604..463f4243 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -259,12 +259,12 @@ spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW spice["msflop_leakage"] = 1 # Leakage power of flop in nW spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF -spice["default_event_rate"] = 100 # Default event activity of every gate. MHz -spice["flop_transisition_prob"] = .5 # Transition probability of inverter. -spice["inv_transisition_prob"] = .5 # Transition probability of inverter. -spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand. -spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand. -spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor. +spice["default_event_rate"] = 100 # Default event activity of every gate. MHz +spice["flop_transition_prob"] = .5 # Transition probability of inverter. +spice["inv_transition_prob"] = .5 # Transition probability of inverter. +spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand. +spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. +spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. ################################################### ##END Spice Simulation Parameters ###################################################