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Fix error in when to add vias for array power

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mrg
2020-06-29 15:28:55 -07:00
parent 4e7e0c5954
commit bec948dcc3
2 changed files with 9 additions and 3 deletions
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compiler/modules/replica_column.py
+4 -2
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@@ -184,9 +184,11 @@ class replica_column(design.design):
height=wl_pin.height())
# Supplies are only connected in the ends
for inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
for (index, inst) in self.cell_inst.items():
for pin_name in ["vdd", "gnd"]:
if pin_name in inst.mod.pins:
if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
self.copy_power_pins(inst, pin_name)
else:
self.copy_layout_pin(inst, pin_name)
def get_bitcell_pins(self, col, row):