diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py
index 09a014ce..0c7e412e 100644
--- a/compiler/modules/replica_bitcell_array.py
+++ b/compiler/modules/replica_bitcell_array.py
@@ -381,7 +381,7 @@ class replica_bitcell_array(design.design):
         # vdd/gnd are only connected in the perimeter cells
         # replica column should only have a vdd/gnd in the dummy cell on top/bottom
         supply_insts = [self.dummy_col_left_inst, self.dummy_col_right_inst,
-                        self.dummy_row_top_inst, self.dummy_row_bot_inst] + list(self.replica_col_inst.values())
+                        self.dummy_row_top_inst, self.dummy_row_bot_inst]
         for pin_name in ["vdd", "gnd"]:
             for inst in supply_insts:
                 pin_list = inst.get_pins(pin_name)
@@ -390,6 +390,10 @@ class replica_bitcell_array(design.design):
                                        loc=pin.center(),
                                        directions=("V", "V"),
                                        start_layer=pin.layer)
+                    
+            for inst in list(self.replica_col_inst.values()):
+                self.copy_layout_pin(inst, pin_name)
+                self.copy_layout_pin(inst, pin_name)
 
     def get_rbl_wl_name(self, port):
         """ Return the WL for the given RBL port """
diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index 9cd65e57..9613e6fa 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -184,9 +184,11 @@ class replica_column(design.design):
                                     height=wl_pin.height())
 
         # Supplies are only connected in the ends
-        for inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
+        for (index, inst) in self.cell_inst.items():
             for pin_name in ["vdd", "gnd"]:
-                if pin_name in inst.mod.pins:
+                if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
+                    self.copy_power_pins(inst, pin_name)
+                else:
                     self.copy_layout_pin(inst, pin_name)
 
     def get_bitcell_pins(self, col, row):