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trim bitcells and fix replica column excluding

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This commit is contained in:
Jesse Cirimelli-Low
2023-08-10 00:34:16 -07:00
parent 3fc2a1e229
commit be72bcfa01
2 changed files with 4 additions and 4 deletions
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compiler/modules/bitcell_array.py
+3 -3
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@@ -67,9 +67,9 @@ class bitcell_array(bitcell_base_array):
self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.row_size, num_cols=self.column_size,name_template="bit_r{0}_c{1}")
self.pattern.connect_array()
#for key in self.cell_inst.keys():
# if key != (0,0):
# self.trim_insts.add(self.cell_inst[key].name)
for key in self.cell_inst.keys():
if key != (0,0):
self.trim_insts.add(self.cell_inst[key].name)
def analytical_power(self, corner, load):
"""Power of Bitcell array and bitline in nW."""