From be72bcfa011c66a1473d1bec6741c6acd505aa45 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Thu, 10 Aug 2023 00:34:16 -0700 Subject: [PATCH] trim bitcells and fix replica column excluding --- compiler/modules/bitcell_array.py | 6 +++--- compiler/modules/replica_column.py | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 319691ba..582829cf 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -67,9 +67,9 @@ class bitcell_array(bitcell_base_array): self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.row_size, num_cols=self.column_size,name_template="bit_r{0}_c{1}") self.pattern.connect_array() - #for key in self.cell_inst.keys(): - # if key != (0,0): - # self.trim_insts.add(self.cell_inst[key].name) + for key in self.cell_inst.keys(): + if key != (0,0): + self.trim_insts.add(self.cell_inst[key].name) def analytical_power(self, corner, load): """Power of Bitcell array and bitline in nW.""" diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 84f8f1c6..c6cdd492 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -180,4 +180,4 @@ class replica_column(bitcell_base_array): for row, cell in enumerate(self.cell_inst): if row != self.replica_bit: - self.graph_inst_exclude.add(cell) + self.graph_inst_exclude.add(self.cell_inst[cell])