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Remove RBL label at top level of SRAM

This commit is contained in:
mrg 2020-08-25 14:42:21 -07:00
parent 856cce1e62
commit bd8bf9afd8
2 changed files with 4 additions and 2 deletions
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2
compiler/modules/bank.py
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@ -68,7 +68,7 @@ class bank(design.design):
self.route_layout() self.route_layout()
# Can remove the following, but it helps for debug! # Can remove the following, but it helps for debug!
self.add_lvs_correspondence_points() # self.add_lvs_correspondence_points()
# Remember the bank center for further placement # Remember the bank center for further placement
self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1) self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1)

4
compiler/sram/sram_1bank.py
View File

@ -260,6 +260,8 @@ class sram_1bank(sram_base):
for signal in self.control_logic_inputs[port]: for signal in self.control_logic_inputs[port]:
if signal == "clk": if signal == "clk":
continue continue
if signal.startswith("rbl"):
continue
if OPTS.perimeter_pins: if OPTS.perimeter_pins:
self.add_perimeter_pin(name=signal + "{}".format(port), self.add_perimeter_pin(name=signal + "{}".format(port),
pin=self.control_logic_insts[port].get_pin(signal), pin=self.control_logic_insts[port].get_pin(signal),
@ -590,7 +592,7 @@ class sram_1bank(sram_base):
These should probably be turned off by default though, since extraction These should probably be turned off by default though, since extraction
will show these as ports in the extracted netlist. will show these as ports in the extracted netlist.
""" """
return
for n in self.control_logic_outputs[0]: for n in self.control_logic_outputs[0]:
pin = self.control_logic_insts[0].get_pin(n) pin = self.control_logic_insts[0].get_pin(n)
self.add_label(text=n, self.add_label(text=n,