From bd8bf9afd834e97bc8ec4125cc0a82ac0534d923 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 Aug 2020 14:42:21 -0700 Subject: [PATCH] Remove RBL label at top level of SRAM --- compiler/modules/bank.py | 2 +- compiler/sram/sram_1bank.py | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index c972eb2a..c5c02869 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -68,7 +68,7 @@ class bank(design.design): self.route_layout() # Can remove the following, but it helps for debug! - self.add_lvs_correspondence_points() + # self.add_lvs_correspondence_points() # Remember the bank center for further placement self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 752d23c0..af1b7a2b 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -260,6 +260,8 @@ class sram_1bank(sram_base): for signal in self.control_logic_inputs[port]: if signal == "clk": continue + if signal.startswith("rbl"): + continue if OPTS.perimeter_pins: self.add_perimeter_pin(name=signal + "{}".format(port), pin=self.control_logic_insts[port].get_pin(signal), @@ -590,7 +592,7 @@ class sram_1bank(sram_base): These should probably be turned off by default though, since extraction will show these as ports in the extracted netlist. """ - + return for n in self.control_logic_outputs[0]: pin = self.control_logic_insts[0].get_pin(n) self.add_label(text=n,