mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'supply_router' into dev
This commit is contained in:
commit
bc8fd4a882
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@ -57,6 +57,12 @@ class design(hierarchy_design):
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self.cell_name,
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self.cell_name,
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GDS["unit"])
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GDS["unit"])
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# Convert names back to the original names
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# so that copying will use the new names
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for pin_name in self.pin_map:
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for index1, pin in enumerate(self.pin_map[pin_name]):
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self.pin_map[pin_name][index1].name = self.get_original_pin_name(pin.name)
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self.width = width
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self.width = width
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self.height = height
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self.height = height
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@ -1235,7 +1235,6 @@ class layout():
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self.add_power_pin(new_name, pin.center(), start_layer=start_layer)
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self.add_power_pin(new_name, pin.center(), start_layer=start_layer)
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def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
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def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
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# Hack for min area
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# Hack for min area
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if OPTS.tech_name == "sky130":
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if OPTS.tech_name == "sky130":
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min_area = drc["minarea_{}".format(self.pwr_grid_layer)]
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min_area = drc["minarea_{}".format(self.pwr_grid_layer)]
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@ -27,13 +27,13 @@ class pin_group:
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# Flag for when it is enclosed
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# Flag for when it is enclosed
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self.enclosed = False
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self.enclosed = False
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# Remove any redundant pins (i.e. contained in other pins)
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irredundant_pin_set = self.remove_redundant_shapes(list(pin_set))
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# This is a list because we can have a pin
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# This is a list because we can have a pin
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# group of disconnected sets of pins
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# group of disconnected sets of pins
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# and these are represented by separate lists
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# and these are represented by separate lists
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self.pins = set(irredundant_pin_set)
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self.pins = set(pin_set)
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# Remove any redundant pins (i.e. contained in other pins)
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self.remove_redundant_pins()
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self.router = router
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self.router = router
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# These are the corresponding pin grids for each pin group.
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# These are the corresponding pin grids for each pin group.
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@ -68,6 +68,10 @@ class pin_group:
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total_string += ")"
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total_string += ")"
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return total_string
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return total_string
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def add_pin(self, pin):
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self.pins.add(pin)
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self.remove_redundant_pins()
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def __repr__(self):
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def __repr__(self):
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""" override repr function output """
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""" override repr function output """
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return str(self)
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return str(self)
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@ -81,6 +85,13 @@ class pin_group:
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def is_routed(self):
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def is_routed(self):
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return self.routed
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return self.routed
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def remove_redundant_pins(self):
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"""
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Remove redundant pin shapes
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"""
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new_pin_list = self.remove_redundant_shapes(list(self.pins))
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self.pins = set(new_pin_list)
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def remove_redundant_shapes(self, pin_list):
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def remove_redundant_shapes(self, pin_list):
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"""
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"""
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Remove any pin layout that is contained within another.
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Remove any pin layout that is contained within another.
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@ -90,7 +101,6 @@ class pin_group:
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if local_debug:
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if local_debug:
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debug.info(0, "INITIAL: {}".format(pin_list))
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debug.info(0, "INITIAL: {}".format(pin_list))
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# Make a copy of the list to start
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new_pin_list = pin_list.copy()
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new_pin_list = pin_list.copy()
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remove_indices = set()
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remove_indices = set()
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@ -824,8 +824,7 @@ class router(router_tech):
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group_map[gid] = pin_group(name=pin_name,
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group_map[gid] = pin_group(name=pin_name,
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pin_set=[],
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pin_set=[],
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router=self)
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router=self)
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# We always add it to the first set since they are touching
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group_map[gid].add_pin(pin)
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group_map[gid].pins.add(pin)
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self.pin_groups[pin_name] = list(group_map.values())
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self.pin_groups[pin_name] = list(group_map.values())
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@ -23,7 +23,6 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
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globals.init_openram(config_file)
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globals.init_openram(config_file)
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from sram_config import sram_config
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from sram_config import sram_config
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OPTS.route_supplies = False
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OPTS.num_rw_ports = 1
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_w_ports = 0
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@ -23,7 +23,6 @@ class sram_1bank_2mux_global_test(openram_test):
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globals.init_openram(config_file)
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globals.init_openram(config_file)
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from sram_config import sram_config
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from sram_config import sram_config
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OPTS.local_array_size = 8
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OPTS.local_array_size = 8
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OPTS.route_supplies = False
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c = sram_config(word_size=8,
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c = sram_config(word_size=8,
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num_words=32,
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num_words=32,
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num_banks=1)
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num_banks=1)
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@ -33,7 +33,6 @@ class sram_1bank_2mux_func_test(openram_test):
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from characterizer import functional
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from characterizer import functional
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from sram_config import sram_config
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from sram_config import sram_config
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OPTS.local_array_size = 8
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OPTS.local_array_size = 8
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OPTS.route_supplies = False
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c = sram_config(word_size=8,
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c = sram_config(word_size=8,
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num_words=32,
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num_words=32,
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num_banks=1)
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num_banks=1)
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