diff --git a/compiler/base/design.py b/compiler/base/design.py
index 0a5a8a97..8c621742 100644
--- a/compiler/base/design.py
+++ b/compiler/base/design.py
@@ -57,6 +57,12 @@ class design(hierarchy_design):
                                                   self.cell_name,
                                                   GDS["unit"])
 
+            # Convert names back to the original names
+            # so that copying will use the new names
+            for pin_name in self.pin_map:
+                for index1, pin in enumerate(self.pin_map[pin_name]):
+                    self.pin_map[pin_name][index1].name = self.get_original_pin_name(pin.name)
+
             self.width = width
             self.height = height
 
diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index 9b8fa6f8..fad5c8ae 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -1235,7 +1235,6 @@ class layout():
         self.add_power_pin(new_name, pin.center(), start_layer=start_layer)
 
     def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
-
         # Hack for min area
         if OPTS.tech_name == "sky130":
             min_area = drc["minarea_{}".format(self.pwr_grid_layer)]
diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py
index d46ab320..01a8b074 100644
--- a/compiler/router/pin_group.py
+++ b/compiler/router/pin_group.py
@@ -27,13 +27,13 @@ class pin_group:
         # Flag for when it is enclosed
         self.enclosed = False
 
-        # Remove any redundant pins (i.e. contained in other pins)
-        irredundant_pin_set = self.remove_redundant_shapes(list(pin_set))
-
         # This is a list because we can have a pin
         # group of disconnected sets of pins
         # and these are represented by separate lists
-        self.pins = set(irredundant_pin_set)
+        self.pins = set(pin_set)
+        # Remove any redundant pins (i.e. contained in other pins)
+        self.remove_redundant_pins()
+
 
         self.router = router
         # These are the corresponding pin grids for each pin group.
@@ -68,6 +68,10 @@ class pin_group:
         total_string += ")"
         return total_string
 
+    def add_pin(self, pin):
+        self.pins.add(pin)
+        self.remove_redundant_pins()
+        
     def __repr__(self):
         """ override repr function output """
         return str(self)
@@ -81,6 +85,13 @@ class pin_group:
     def is_routed(self):
         return self.routed
 
+    def remove_redundant_pins(self):
+        """
+        Remove redundant pin shapes
+        """
+        new_pin_list = self.remove_redundant_shapes(list(self.pins))
+        self.pins = set(new_pin_list)
+
     def remove_redundant_shapes(self, pin_list):
         """
         Remove any pin layout that is contained within another.
@@ -90,7 +101,6 @@ class pin_group:
         if local_debug:
             debug.info(0, "INITIAL: {}".format(pin_list))
 
-        # Make a copy of the list to start
         new_pin_list = pin_list.copy()
 
         remove_indices = set()
diff --git a/compiler/router/router.py b/compiler/router/router.py
index dcccfe61..cd20d858 100644
--- a/compiler/router/router.py
+++ b/compiler/router/router.py
@@ -824,8 +824,7 @@ class router(router_tech):
                 group_map[gid] = pin_group(name=pin_name,
                                            pin_set=[],
                                            router=self)
-            # We always add it to the first set since they are touching
-            group_map[gid].pins.add(pin)
+            group_map[gid].add_pin(pin)
 
         self.pin_groups[pin_name] = list(group_map.values())
 
diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
index 11ac6673..af97d25a 100755
--- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
@@ -23,7 +23,6 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
-        OPTS.route_supplies = False
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
diff --git a/compiler/tests/20_sram_1bank_2mux_global_test.py b/compiler/tests/20_sram_1bank_2mux_global_test.py
index 0d80adf9..11f084ec 100755
--- a/compiler/tests/20_sram_1bank_2mux_global_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_global_test.py
@@ -23,7 +23,6 @@ class sram_1bank_2mux_global_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
         OPTS.local_array_size = 8
-        OPTS.route_supplies = False
         c = sram_config(word_size=8,
                         num_words=32,
                         num_banks=1)
diff --git a/compiler/tests/22_sram_1bank_2mux_global_func_test.py b/compiler/tests/22_sram_1bank_2mux_global_func_test.py
index b18f9734..3a085adc 100755
--- a/compiler/tests/22_sram_1bank_2mux_global_func_test.py
+++ b/compiler/tests/22_sram_1bank_2mux_global_func_test.py
@@ -33,7 +33,6 @@ class sram_1bank_2mux_func_test(openram_test):
         from characterizer import functional
         from sram_config import sram_config
         OPTS.local_array_size = 8
-        OPTS.route_supplies = False
         c = sram_config(word_size=8,
                         num_words=32,
                         num_banks=1)