luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Use internal name for col/row caps. gds ordered read enabled.

This commit is contained in:
mrg 2020-12-03 10:03:47 -08:00
parent 28354bffe0
commit bad1274bdb
4 changed files with 7 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
compiler/modules/col_cap_array.py
View File

@ -100,7 +100,7 @@ class col_cap_array(bitcell_base_array):
inst = self.cell_inst[row, col] inst = self.cell_inst[row, col]
for pin_name in ["vdd", "gnd"]: for pin_name in ["vdd", "gnd"]:
for pin in inst.get_pins(pin_name): for pin in inst.get_pins(pin_name):
self.add_power_pin(name=pin.name, self.add_power_pin(name=pin_name,
loc=pin.center(), loc=pin.center(),
start_layer=pin.layer) start_layer=pin.layer)

2
compiler/modules/row_cap_array.py
View File

@ -113,7 +113,7 @@ class row_cap_array(bitcell_base_array):
inst = self.cell_inst[row, col] inst = self.cell_inst[row, col]
for pin_name in ["vdd", "gnd"]: for pin_name in ["vdd", "gnd"]:
for pin in inst.get_pins(pin_name): for pin in inst.get_pins(pin_name):
self.add_power_pin(name=pin.name, self.add_power_pin(name=pin_name,
loc=pin.center(), loc=pin.center(),
start_layer=pin.layer) start_layer=pin.layer)

10
compiler/verify/calibre.py
View File

@ -103,10 +103,10 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out
'cmnTranscriptEchoToFile': 1, 'cmnTranscriptEchoToFile': 1,
'lvsRecognizeGates': 'NONE', 'lvsRecognizeGates': 'NONE',
} }
# FIXME: Remove when vdd/gnd connected # FIXME: Remove when vdd/gnd connected
#'cmnVConnectNamesState' : 'ALL', #connects all nets with the same namee # 'cmnVConnectNamesState' : 'ALL', #connects all nets with the same namee
# FIXME: Remove when vdd/gnd connected # FIXME: Remove when vdd/gnd connected
#'lvsAbortOnSupplyError' : 0 # 'lvsAbortOnSupplyError' : 0
if not final_verification or not OPTS.route_supplies: if not final_verification or not OPTS.route_supplies:
lvs_runset['cmnVConnectReport']=1 lvs_runset['cmnVConnectReport']=1
@ -115,8 +115,6 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out
else: else:
lvs_runset['lvsAbortOnSupplyError']=1 lvs_runset['lvsAbortOnSupplyError']=1
# write the runset file # write the runset file
f = open(output_path + "lvs_runset", "w") f = open(output_path + "lvs_runset", "w")
for k in sorted(iter(lvs_runset.keys())): for k in sorted(iter(lvs_runset.keys())):

1
compiler/verify/magic.py
View File

@ -89,6 +89,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
f.write("gds warning default\n") f.write("gds warning default\n")
f.write("gds flatten true\n") f.write("gds flatten true\n")
f.write("gds readonly true\n") f.write("gds readonly true\n")
f.write("gds ordering true\n")
f.write("gds read {}\n".format(gds_name)) f.write("gds read {}\n".format(gds_name))
f.write('puts "Finished reading gds {}"\n'.format(gds_name)) f.write('puts "Finished reading gds {}"\n'.format(gds_name))
f.write("load {}\n".format(cell_name)) f.write("load {}\n".format(cell_name))