Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.

compiler/base/design.py

@@ -30,6 +30,8 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
         # These modules ensure unique names or have no changes if they
         # aren't unique
         ok_list = ['ms_flop.ms_flop',
+                   'dff.dff',
+                   'dff_buf.dff_buf',
                    'bitcell.bitcell',
                    'contact.contact',
                    'ptx.ptx',

compiler/base/hierarchy_spice.py

@@ -91,6 +91,8 @@ class spice(verilog.verilog):
         group of modules are generated."""
 
         if (check and (len(self.insts[-1].mod.pins) != len(args))):
+            debug.error("Connections: {}".format(self.insts[-1].mod.pins))
+            debug.error("Connections: {}".format(args))
             debug.error("Number of net connections ({0}) does not match last instance ({1})".format(len(self.insts[-1].mod.pins),
                                                                                                     len(args)), 1)
         self.conns.append(args)