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merging changes with pbitcell_array test

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Michael Timothy Grimes
2018-07-12 23:51:44 -07:00
parent a64ca423c6 7d8352a04d
commit ba43b986ae
85 changed files with 1181 additions and 1076 deletions
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compiler/tests/05_pbitcell_array_test.py
+9 -8
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@@ -11,27 +11,26 @@ import globals
from globals import OPTS
import debug
#@unittest.skip("SKIPPING 05_array_multiport_test")
class array_multiport_test(openram_test):
#@unittest.skip("SKIPPING 05_pbitcell_array_test")
class pbitcell_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import bitcell_array
debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
OPTS.bitcell = "pbitcell"
OPTS.rw_ports = 2
OPTS.r_ports = 2
OPTS.w_ports = 2
debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
self.local_check(a)
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
OPTS.bitcell = "pbitcell"
OPTS.rw_ports = 2
OPTS.r_ports = 0
OPTS.w_ports = 2
@@ -47,10 +46,12 @@ class array_multiport_test(openram_test):
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
self.local_check(a)
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
self.local_check(a)
OPTS.bitcell = "bitcell"
OPTS.check_lvsdrc = True
globals.end_openram()
OPTS.bitcell = "bitcell"
# instantiate a copy of the class to actually run the test
if __name__ == "__main__":