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Add psram 1w/1r test. Fix bl/br port naming errors in bank.

This commit is contained in:
Matt Guthaus 2018-11-16 15:31:22 -08:00
parent 8f28f4fde5
commit b89c011e41
2 changed files with 76 additions and 29 deletions
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61
compiler/modules/bank.py
View File

@ -877,9 +877,9 @@ class bank(design.design):
if self.col_addr_size==0: if self.col_addr_size==0:
return return
bottom_inst = self.column_mux_array_inst[port] inst1 = self.column_mux_array_inst[port]
top_inst = self.precharge_array_inst[port] inst2 = self.precharge_array_inst[port]
self.connect_bitlines(top_inst, bottom_inst, self.num_cols) self.connect_bitlines(inst1, inst2, self.num_cols)
def route_column_mux_to_bitcell_array(self, port): def route_column_mux_to_bitcell_array(self, port):
""" Routing of BL and BR between col mux bitcell array """ """ Routing of BL and BR between col mux bitcell array """
@ -888,47 +888,50 @@ class bank(design.design):
if self.col_addr_size==0: if self.col_addr_size==0:
return return
bottom_inst = self.column_mux_array_inst[port] inst2 = self.column_mux_array_inst[port]
top_inst = self.bitcell_array_inst inst1 = self.bitcell_array_inst
self.connect_bitlines(top_inst, bottom_inst, self.num_cols) inst1_bl_name = self.bl_names[port]+"_{}"
inst1_br_name = self.br_names[port]+"_{}"
self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.num_cols,
inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name)
def route_sense_amp_to_column_mux_or_precharge_array(self, port): def route_sense_amp_to_column_mux_or_precharge_array(self, port):
""" Routing of BL and BR between sense_amp and column mux or precharge array """ """ Routing of BL and BR between sense_amp and column mux or precharge array """
bottom_inst = self.sense_amp_array_inst[port] inst2 = self.sense_amp_array_inst[port]
if self.col_addr_size>0: if self.col_addr_size>0:
# Sense amp is connected to the col mux # Sense amp is connected to the col mux
top_inst = self.column_mux_array_inst[port] inst1 = self.column_mux_array_inst[port]
top_bl = "bl_out_{}" inst1_bl_name = "bl_out_{}"
top_br = "br_out_{}" inst1_br_name = "br_out_{}"
else: else:
# Sense amp is directly connected to the precharge array # Sense amp is directly connected to the precharge array
top_inst = self.precharge_array_inst[port] inst1 = self.precharge_array_inst[port]
top_bl = "bl_{}" inst1_bl_name = "bl_{}"
top_br = "br_{}" inst1_br_name = "br_{}"
self.connect_bitlines(inst1=top_inst, inst2=bottom_inst, num_bits=self.word_size, self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
inst1_bl_name=top_bl, inst1_br_name=top_br) inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name)
def route_write_driver_to_column_mux_or_precharge_array(self, port): def route_write_driver_to_column_mux_or_bitcell_array(self, port):
""" Routing of BL and BR between sense_amp and column mux or precharge array """ """ Routing of BL and BR between sense_amp and column mux or bitcell array """
bottom_inst = self.write_driver_array_inst[port] inst2 = self.write_driver_array_inst[port]
if self.col_addr_size>0: if self.col_addr_size>0:
# Sense amp is connected to the col mux # Write driver is connected to the col mux
top_inst = self.column_mux_array_inst[port] inst1 = self.column_mux_array_inst[port]
top_bl = "bl_out_{}" inst1_bl_name = "bl_out_{}"
top_br = "br_out_{}" inst1_br_name = "br_out_{}"
else: else:
# Sense amp is directly connected to the precharge array # Write driver is directly connected to the bitcell array
top_inst = self.precharge_array_inst[port] inst1 = self.bitcell_array_inst
top_bl = "bl_{}" inst1_bl_name = self.bl_names[port]+"_{}"
top_br = "br_{}" inst1_br_name = self.br_names[port]+"_{}"
self.connect_bitlines(inst1=top_inst, inst2=bottom_inst, num_bits=self.word_size, self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
inst1_bl_name=top_bl, inst1_br_name=top_br) inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name)
def route_write_driver_to_sense_amp(self, port): def route_write_driver_to_sense_amp(self, port):
""" Routing of BL and BR between write driver and sense amp """ """ Routing of BL and BR between write driver and sense amp """
@ -943,7 +946,7 @@ class bank(design.design):
for bit in range(self.word_size): for bit in range(self.word_size):
data_pin = self.sense_amp_array_inst[port].get_pin("data_{}".format(bit)) data_pin = self.sense_amp_array_inst[port].get_pin("data_{}".format(bit))
self.add_layout_pin_rect_center(text="dout{0}_{1}".format(self.read_ports[port],bit), self.add_layout_pin_rect_center(text="dout{0}_{1}".format(port,bit),
layer=data_pin.layer, layer=data_pin.layer,
offset=data_pin.center(), offset=data_pin.center(),
height=data_pin.height(), height=data_pin.height(),

44
compiler/tests/20_psram_1bank_2mux_1w_1r_test.py Executable file
View File

@ -0,0 +1,44 @@
#!/usr/bin/env python3
"""
Run a regression test on a 1 bank SRAM
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
class psram_1bank_2mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.num_rw_ports = 0
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1
c = sram_config(word_size=4,
num_words=32,
num_banks=1)
c.num_words=32
c.words_per_row=2
debug.info(1, "Single bank two way column mux 1w/1r with control logic")
a = sram(c, "sram")
self.local_check(a, final_verification=True)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()