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decoder drc clean

This commit is contained in:
jcirimel 2020-08-19 00:39:55 -07:00
parent e7c9914d77
commit b7ef5496c4
2 changed files with 7 additions and 0 deletions
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3
compiler/modules/hierarchical_decoder.py
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@ -595,6 +595,9 @@ class hierarchical_decoder(design.design):
mid_point2 = vector(x_offset, y_offset) mid_point2 = vector(x_offset, y_offset)
rail_pos = vector(self.predecode_bus[rail_name].cx(), mid_point2.y) rail_pos = vector(self.predecode_bus[rail_name].cx(), mid_point2.y)
self.add_path(self.output_layer, [pin_pos, mid_point1, mid_point2, rail_pos]) self.add_path(self.output_layer, [pin_pos, mid_point1, mid_point2, rail_pos])
if OPTS.tech_name == "sky130":
above_rail = vector(self.predecode_bus[rail_name].cx(), mid_point2.y + (self.cell_height/2))
self.add_path(self.bus_layer, [rail_pos, above_rail], width = self.li_width + self.m1_enclose_mcon * 2)
# pin_pos = pin.center() # pin_pos = pin.center()
# rail_pos = vector(self.predecode_bus[rail_name].cx(), pin_pos.y) # rail_pos = vector(self.predecode_bus[rail_name].cx(), pin_pos.y)

4
compiler/modules/hierarchical_predecode.py
View File

@ -274,6 +274,10 @@ class hierarchical_predecode(design.design):
height=via.mod.second_layer_height, height=via.mod.second_layer_height,
width=via.mod.second_layer_width) width=via.mod.second_layer_width)
if OPTS.tech_name == "sky130":
below_rail = vector(self.decode_rails[out_pin].cx(), y_offset - (self.cell_height/2))
self.add_path(self.bus_layer, [rail_pos, below_rail], width = self.li_width + self.m1_enclose_mcon * 2)
def route_and_to_rails(self): def route_and_to_rails(self):
# This 2D array defines the connection mapping # This 2D array defines the connection mapping
and_input_line_combination = self.get_and_input_line_combination() and_input_line_combination = self.get_and_input_line_combination()