From b7ef5496c4cfa32fa26eafa441cc12d1aa272639 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Wed, 19 Aug 2020 00:39:55 -0700 Subject: [PATCH] decoder drc clean --- compiler/modules/hierarchical_decoder.py | 3 +++ compiler/modules/hierarchical_predecode.py | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index dbacd051..80cdfb1c 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -595,6 +595,9 @@ class hierarchical_decoder(design.design): mid_point2 = vector(x_offset, y_offset) rail_pos = vector(self.predecode_bus[rail_name].cx(), mid_point2.y) self.add_path(self.output_layer, [pin_pos, mid_point1, mid_point2, rail_pos]) + if OPTS.tech_name == "sky130": + above_rail = vector(self.predecode_bus[rail_name].cx(), mid_point2.y + (self.cell_height/2)) + self.add_path(self.bus_layer, [rail_pos, above_rail], width = self.li_width + self.m1_enclose_mcon * 2) # pin_pos = pin.center() # rail_pos = vector(self.predecode_bus[rail_name].cx(), pin_pos.y) diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index a89f5fa6..1645d0d1 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -274,6 +274,10 @@ class hierarchical_predecode(design.design): height=via.mod.second_layer_height, width=via.mod.second_layer_width) + if OPTS.tech_name == "sky130": + below_rail = vector(self.decode_rails[out_pin].cx(), y_offset - (self.cell_height/2)) + self.add_path(self.bus_layer, [rail_pos, below_rail], width = self.li_width + self.m1_enclose_mcon * 2) + def route_and_to_rails(self): # This 2D array defines the connection mapping and_input_line_combination = self.get_and_input_line_combination()