mirror of https://github.com/VLSIDA/OpenRAM.git
186 lines
7.8 KiB
Python
186 lines
7.8 KiB
Python
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California
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# All rights reserved.
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#
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import debug
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import geometry
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from sram_factory import factory
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from bitcell_base_array import bitcell_base_array
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from globals import OPTS
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from tech import layer
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class sky130_bitcell_base_array(bitcell_base_array):
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"""
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Abstract base class for bitcell-arrays -- bitcell, dummy, replica
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"""
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def __init__(self, name, rows, cols, column_offset):
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super().__init__(name, rows, cols, column_offset)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def place_array(self, name_template, row_offset=0, col_offset=0):
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yoffset = 0.0
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for row in range(0, len(self.array_layout)):
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xoffset = 0.0
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for col in range(0, len(self.array_layout[row])):
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self.place_inst = self.insts[(col) + (row) * len(self.array_layout[row])]
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if row % 2 == 0:
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if col == 0:
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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elif col % 4 == 0:
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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elif col % 4 == 3 :
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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elif col % 4 == 2:
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self.place_inst.place(offset=[xoffset + self.cell.width, yoffset + self.cell.height], mirror="XY")
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else:
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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else:
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if col == 0:
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self.place_inst.place(offset=[xoffset, yoffset])
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elif col % 4 == 0:
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self.place_inst.place(offset=[xoffset, yoffset])
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elif col % 4 == 3 :
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self.place_inst.place(offset=[xoffset, yoffset])
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elif col % 4 == 2:
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self.place_inst.place(offset=[xoffset + self.cell.width, yoffset], mirror="MY")
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# self.place_inst.place(offset=[xoffset, yoffset])
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else:
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self.place_inst.place(offset=[xoffset, yoffset])
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xoffset += self.place_inst.width
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yoffset += self.place_inst.height
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self.width = max([x.rx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts])
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def get_bitcell_pins(self, row, col, swap = False):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = []
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for port in self.all_ports:
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bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
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if swap:
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swap_pins = []
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for pin in bitcell_pins:
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if "bl" in pin:
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swap_pins.append(pin.replace("bl", "br"))
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elif "br" in pin:
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swap_pins.append(pin.replace("br", "bl"))
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bitcell_pins = swap_pins
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bitcell_pins.append("gnd") # gnd
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bitcell_pins.append("vdd") # vdd
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bitcell_pins.append("vdd") # vpb
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bitcell_pins.append("gnd") # vnb
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bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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return bitcell_pins
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def get_strap_pins(self, row, col, name=""):
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"""
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Creates a list of connections in the strap cell,
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indexed by column and row, for instance use in bitcell_array
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"""
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if name and "_p" in name:
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strap_pins = ["gnd"]
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else:
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strap_pins = ["vdd"]
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return strap_pins
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def get_col_cap_p_pins(self, row, col):
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"""
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"""
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strap_pins = ["gnd", "vdd", "gnd"]
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return strap_pins
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def get_col_cap_pins(self, row, col):
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"""
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"""
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strap_pins = []
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for port in self.all_ports:
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strap_pins.extend([x for x in self.get_bitline_names(port) if "bl" in x and x.endswith("_{0}".format(col))])
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strap_pins.extend(["vdd", "gnd"])
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for port in self.all_ports:
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strap_pins.extend([x for x in self.get_bitline_names(port) if "br" in x and x.endswith("_{0}".format(col))])
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if row == 0:
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strap_pins.extend(["top_gate"])
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else:
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strap_pins.extend(["bot_gate"])
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return strap_pins
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def get_row_cap_pins(self, row, col):
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"""
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"""
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strap_pins = ["gnd", "vdd", "gnd"]
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return strap_pins
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def get_corner_pins(self):
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"""
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"""
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strap_pins = ["vdd", "gnd", "vdd"]
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return strap_pins
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def add_supply_pins(self):
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""" Add the layout pins """
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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if row == 2: #add only 1 label per col
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if 'VPB' in self.cell_inst[row, col].mod.pins:
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pin = inst.get_pin("vpb")
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self.objs.append(geometry.rectangle(layer["nwell"],
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pin.ll(),
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pin.width(),
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pin.height()))
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self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
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if 'VNB' in self.cell_inst[row, col].mod.pins:
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try:
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from tech import layer_override
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if layer_override['VNB']:
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pin = inst.get_pin("vnb")
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self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
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self.objs.append(geometry.rectangle(layer["pwellp"],
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pin.ll(),
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pin.width(),
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pin.height()))
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except:
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pin = inst.get_pin("vnb")
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self.add_label("vdd", pin.layer, pin.center())
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def add_bitline_pins(self):
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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text = "bl_{0}_{1}".format(port, col)
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if "Y" in self.cell_inst[0, col].mirror:
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text = text.replace("bl", "br")
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self.add_layout_pin(text=text,
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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text = "br_{0}_{1}".format(port, col)
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if "Y" in self.cell_inst[0, col].mirror:
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text = text.replace("br", "bl")
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self.add_layout_pin(text=text,
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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