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synced 2026-08-29 09:30:38 +02:00
Use OPTS.precharge instead of hard coded precharge.
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@@ -275,7 +275,7 @@ class port_data(design.design):
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self.br_names = self.bitcell.get_all_br_names()
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self.wl_names = self.bitcell.get_all_wl_names()
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# used for bl/br names
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self.precharge = factory.create(module_type="precharge",
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self.precharge = factory.create(module_type=OPTS.precharge,
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bitcell_bl=self.bl_names[0],
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bitcell_br=self.br_names[0])
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@@ -72,7 +72,7 @@ class precharge_array(design.design):
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self.DRC_LVS()
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def add_modules(self):
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self.pc_cell = factory.create(module_type="precharge",
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self.pc_cell = factory.create(module_type=OPTS.precharge,
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size=self.size,
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bitcell_bl=self.bitcell_bl,
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bitcell_br=self.bitcell_br)
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