From b6f3fbdd1f5d8e79d705f2dfca4908c74d4c005b Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Mar 2021 09:44:14 -0700 Subject: [PATCH] Use OPTS.precharge instead of hard coded precharge. --- compiler/modules/port_data.py | 2 +- compiler/modules/precharge_array.py | 2 +- compiler/options.py | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 8afa8d06..71c8449a 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -275,7 +275,7 @@ class port_data(design.design): self.br_names = self.bitcell.get_all_br_names() self.wl_names = self.bitcell.get_all_wl_names() # used for bl/br names - self.precharge = factory.create(module_type="precharge", + self.precharge = factory.create(module_type=OPTS.precharge, bitcell_bl=self.bl_names[0], bitcell_br=self.br_names[0]) diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 498ba815..8718dfd0 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -72,7 +72,7 @@ class precharge_array(design.design): self.DRC_LVS() def add_modules(self): - self.pc_cell = factory.create(module_type="precharge", + self.pc_cell = factory.create(module_type=OPTS.precharge, size=self.size, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br) diff --git a/compiler/options.py b/compiler/options.py index 4c04cdb0..e3a9a76e 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -171,6 +171,7 @@ class options(optparse.Values): nand2_dec = "pnand2" nand3_dec = "pnand3" nand4_dec = "pnand4" # Not available right now + precharge = "precharge" precharge_array = "precharge_array" ptx = "ptx" replica_bitline = "replica_bitline"