luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-03 08:27:11 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merging branch with PrivateRAM dev

Browse Source
This commit is contained in:
Michael Timothy Grimes
2018-05-18 15:15:31 -07:00
parent 3971835f24 58628d7867
commit b5df0cc30a
84 changed files with 14871 additions and 13447 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/tests/04_pinvbuf_test.py
+36
View File
@@ -0,0 +1,36 @@
#!/usr/bin/env python2.7
"""
Run a regresion test on a 2-row buffer cell
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class pinvbuf_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import pinvbuf
debug.info(2, "Testing inverter/buffer 4x 8x")
a = pinvbuf.pinvbuf(4,8)
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/04_single_level_column_mux_test.py
+39
View File
@@ -0,0 +1,39 @@
#!/usr/bin/env python2.7
"""
Run a regresion test on a wordline_driver array
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
#@unittest.skip("SKIPPING 04_driver_test")
class single_level_column_mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import single_level_column_mux
import tech
debug.info(2, "Checking column mux")
tx = single_level_column_mux.single_level_column_mux(tx_size=8)
self.local_check(tx)
OPTS.check_lvsdrc = True
globals.end_openram()
# instantiate a copy of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/04_wordline_driver_test.py → compiler/tests/08_wordline_driver_test.py
View File
compiler/tests/11_dff_buf_array_test.py
+44
View File
@@ -0,0 +1,44 @@
#!/usr/bin/env python2.7
"""
Run a regresion test on a dff_array.
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class dff_buf_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import dff_buf_array
debug.info(2, "Testing dff_buf_array for 3x3")
a = dff_buf_array.dff_buf_array(rows=3, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_buf_array for 1x3")
a = dff_buf_array.dff_buf_array(rows=1, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_buf_array for 3x1")
a = dff_buf_array.dff_buf_array(rows=3, columns=1)
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/11_dff_buf_test.py
+36
View File
@@ -0,0 +1,36 @@
#!/usr/bin/env python2.7
"""
Run a regresion test on a dff_buf.
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class dff_buf_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import dff_buf
debug.info(2, "Testing dff_buf 4x 8x")
a = dff_buf.dff_buf(4, 8)
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/11_dff_inv_array_test.py
+44
View File
@@ -0,0 +1,44 @@
#!/usr/bin/env python2.7
"""
Run a regresion test on a dff_array.
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class dff_inv_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import dff_inv_array
debug.info(2, "Testing dff_inv_array for 3x3")
a = dff_inv_array.dff_inv_array(rows=3, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_inv_array for 1x3")
a = dff_inv_array.dff_inv_array(rows=1, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_inv_array for 3x1")
a = dff_inv_array.dff_inv_array(rows=3, columns=1)
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/11_dff_inv_test.py
+36
View File
@@ -0,0 +1,36 @@
#!/usr/bin/env python2.7
"""
Run a regresion test on a dff_inv.
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class dff_inv_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import dff_inv
debug.info(2, "Testing dff_inv 4x")
a = dff_inv.dff_inv(4)
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/19_bank_select_test.py
+36
View File
@@ -0,0 +1,36 @@
#!/usr/bin/env python2.7
"""
Run a regresion test on various srams
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class bank_select_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import bank_select
debug.info(1, "No column mux")
a = bank_select.bank_select()
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
# instantiate a copy of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/19_multi_bank_test.py
+3 -4
View File
@@ -33,10 +33,9 @@ class multi_bank_test(openram_test):
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=2, name="bank3")
self.local_check(a)
# Eight way has a short circuit of one column mux select to gnd rail
# debug.info(1, "Eight way column mux")
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="bank4")
# self.local_check(a)
debug.info(1, "Eight way column mux")
a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="bank4")
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
compiler/tests/19_single_bank_test.py
+3 -3
View File
@@ -34,9 +34,9 @@ class single_bank_test(openram_test):
self.local_check(a)
# Eight way has a short circuit of one column mux select to gnd rail
# debug.info(1, "Eight way column mux")
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=1, name="bank4")
# self.local_check(a)
debug.info(1, "Eight way column mux")
a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=1, name="bank4")
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
compiler/tests/23_lib_sram_prune_test.py
+1 -1
View File
@@ -51,7 +51,7 @@ class lib_test(openram_test):
newname = filename.replace(".lib","_pruned.lib")
libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
self.isapproxdiff(libname,golden,0.15)
self.isapproxdiff(libname,golden,0.40)
OPTS.analytical_delay = True
reload(characterizer)
compiler/tests/23_lib_sram_test.py
+1 -1
View File
@@ -50,7 +50,7 @@ class lib_test(openram_test):
for filename in lib_files:
libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
self.isapproxdiff(libname,golden,0.15)
self.isapproxdiff(libname,golden,0.40)
OPTS.analytical_delay = True
OPTS.trim_netlist = True
compiler/tests/golden/sram_2_16_1_freepdk45.lef
+5549 -5477
View File
File diff suppressed because it is too large Load Diff
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
+31 -31
View File
@@ -82,7 +82,7 @@ cell (sram_2_16_1_freepdk45){
leakage_power () {
when : "CSb";
value : 0.00088149731;
value : 0.0008128352;
}
cell_leakage_power : 0;
bus(DATA){
@@ -103,9 +103,9 @@ cell (sram_2_16_1_freepdk45){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
@@ -137,19 +137,19 @@ cell (sram_2_16_1_freepdk45){
"0.061, 0.062, 0.069");
}
cell_fall(CELL_TABLE) {
values("0.429, 0.43, 0.439",\
"0.429, 0.431, 0.439",\
"0.435, 0.436, 0.446");
values("0.067, 0.068, 0.076",\
"0.067, 0.068, 0.077",\
"0.073, 0.074, 0.082");
}
rise_transition(CELL_TABLE) {
values("0.013, 0.015, 0.026",\
"0.013, 0.015, 0.026",\
"0.013, 0.015, 0.026");
"0.014, 0.015, 0.026");
}
fall_transition(CELL_TABLE) {
values("0.029, 0.031, 0.044",\
"0.029, 0.031, 0.044",\
"0.029, 0.031, 0.044");
values("0.023, 0.024, 0.037",\
"0.023, 0.024, 0.037",\
"0.024, 0.024, 0.037");
}
}
}
@@ -165,9 +165,9 @@ cell (sram_2_16_1_freepdk45){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
@@ -199,9 +199,9 @@ cell (sram_2_16_1_freepdk45){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
@@ -232,9 +232,9 @@ cell (sram_2_16_1_freepdk45){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
@@ -265,9 +265,9 @@ cell (sram_2_16_1_freepdk45){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
@@ -298,19 +298,19 @@ cell (sram_2_16_1_freepdk45){
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0173748762222");
values("0.0175059861111");
}
fall_power(scalar){
values("0.0173748762222");
values("0.0175059861111");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0261209913889");
values("0.0218644166667");
}
fall_power(scalar){
values("0.0261209913889");
values("0.0218644166667");
}
}
internal_power(){
@@ -326,20 +326,20 @@ cell (sram_2_16_1_freepdk45){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("0.4295");
values("0.117");
}
fall_constraint(scalar) {
values("0.4295");
values("0.117");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("0.859");
values("0.234");
}
fall_constraint(scalar) {
values("0.859");
values("0.234");
}
}
}
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
+33 -33
View File
@@ -82,7 +82,7 @@ cell (sram_2_16_1_freepdk45){
leakage_power () {
when : "CSb";
value : 0.00088149731;
value : 0.0008128352;
}
cell_leakage_power : 0;
bus(DATA){
@@ -103,9 +103,9 @@ cell (sram_2_16_1_freepdk45){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
@@ -133,23 +133,23 @@ cell (sram_2_16_1_freepdk45){
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.054, 0.055, 0.061",\
"0.055, 0.055, 0.062",\
"0.06, 0.061, 0.067");
"0.055, 0.056, 0.062",\
"0.06, 0.061, 0.068");
}
cell_fall(CELL_TABLE) {
values("0.425, 0.426, 0.436",\
"0.426, 0.427, 0.436",\
"0.432, 0.433, 0.442");
values("0.066, 0.067, 0.075",\
"0.067, 0.068, 0.076",\
"0.072, 0.073, 0.082");
}
rise_transition(CELL_TABLE) {
values("0.013, 0.014, 0.026",\
"0.013, 0.014, 0.026",\
"0.013, 0.015, 0.026",\
"0.013, 0.015, 0.026");
}
fall_transition(CELL_TABLE) {
values("0.027, 0.029, 0.043",\
"0.027, 0.029, 0.043",\
"0.027, 0.029, 0.043");
values("0.023, 0.024, 0.037",\
"0.023, 0.024, 0.037",\
"0.024, 0.024, 0.037");
}
}
}
@@ -165,9 +165,9 @@ cell (sram_2_16_1_freepdk45){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
@@ -199,9 +199,9 @@ cell (sram_2_16_1_freepdk45){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
@@ -232,9 +232,9 @@ cell (sram_2_16_1_freepdk45){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
@@ -265,9 +265,9 @@ cell (sram_2_16_1_freepdk45){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
@@ -298,19 +298,19 @@ cell (sram_2_16_1_freepdk45){
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0158174252672");
values("0.0159801855389");
}
fall_power(scalar){
values("0.0158174252672");
values("0.0159801855389");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0181396362394");
values("0.0171325605389");
}
fall_power(scalar){
values("0.0181396362394");
values("0.0171325605389");
}
}
internal_power(){
@@ -326,20 +326,20 @@ cell (sram_2_16_1_freepdk45){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("0.4295");
values("0.1125");
}
fall_constraint(scalar) {
values("0.4295");
values("0.1125");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("0.859");
values("0.225");
}
fall_constraint(scalar) {
values("0.859");
values("0.225");
}
}
}
compiler/tests/golden/sram_2_16_1_scn3me_subm.lef
+5435 -5375
View File
File diff suppressed because it is too large Load Diff
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib
+32 -32
View File
@@ -82,7 +82,7 @@ cell (sram_2_16_1_scn3me_subm){
leakage_power () {
when : "CSb";
value : 0.0011563287;
value : 0.0004764706;
}
cell_leakage_power : 0;
bus(DATA){
@@ -108,9 +108,9 @@ cell (sram_2_16_1_scn3me_subm){
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
@@ -132,24 +132,24 @@ cell (sram_2_16_1_scn3me_subm){
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.473, 0.519, 0.888",\
"0.476, 0.522, 0.891",\
"0.516, 0.56, 0.928");
values("0.474, 0.52, 0.888",\
"0.477, 0.522, 0.892",\
"0.517, 0.561, 0.929");
}
cell_fall(CELL_TABLE) {
values("0.582, 0.655, 1.256",\
"0.585, 0.658, 1.259",\
"0.625, 0.697, 1.295");
values("0.582, 0.658, 1.26",\
"0.586, 0.661, 1.262",\
"0.626, 0.7, 1.298");
}
rise_transition(CELL_TABLE) {
values("0.154, 0.233, 1.086",\
"0.155, 0.234, 1.086",\
"0.158, 0.237, 1.086");
values("0.155, 0.233, 1.087",\
"0.156, 0.235, 1.086",\
"0.16, 0.239, 1.086");
}
fall_transition(CELL_TABLE) {
values("0.278, 0.359, 1.499",\
"0.278, 0.361, 1.499",\
"0.28, 0.367, 1.5");
values("0.277, 0.356, 1.502",\
"0.278, 0.358, 1.501",\
"0.279, 0.363, 1.5");
}
}
}
@@ -170,9 +170,9 @@ cell (sram_2_16_1_scn3me_subm){
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
@@ -204,9 +204,9 @@ cell (sram_2_16_1_scn3me_subm){
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
@@ -237,9 +237,9 @@ cell (sram_2_16_1_scn3me_subm){
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
@@ -270,9 +270,9 @@ cell (sram_2_16_1_scn3me_subm){
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
@@ -298,19 +298,19 @@ cell (sram_2_16_1_scn3me_subm){
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("4.91866674167");
values("4.92665");
}
fall_power(scalar){
values("4.91866674167");
values("4.92665");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("5.72315586111");
values("5.74515833333");
}
fall_power(scalar){
values("5.72315586111");
values("5.74515833333");
}
}
internal_power(){
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib
+32 -32
View File
@@ -82,7 +82,7 @@ cell (sram_2_16_1_scn3me_subm){
leakage_power () {
when : "CSb";
value : 0.0011563287;
value : 0.0004764706;
}
cell_leakage_power : 0;
bus(DATA){
@@ -108,9 +108,9 @@ cell (sram_2_16_1_scn3me_subm){
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
@@ -132,24 +132,24 @@ cell (sram_2_16_1_scn3me_subm){
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.458, 0.503, 0.87",\
"0.461, 0.505, 0.873",\
"0.5, 0.544, 0.911");
values("0.458, 0.504, 0.871",\
"0.461, 0.506, 0.874",\
"0.5, 0.544, 0.912");
}
cell_fall(CELL_TABLE) {
values("0.573, 0.645, 1.246",\
"0.576, 0.648, 1.249",\
"0.616, 0.687, 1.286");
values("0.573, 0.649, 1.251",\
"0.577, 0.652, 1.254",\
"0.618, 0.69, 1.29");
}
rise_transition(CELL_TABLE) {
values("0.153, 0.232, 1.084",\
"0.153, 0.233, 1.084",\
"0.156, 0.236, 1.084");
values("0.153, 0.233, 1.085",\
"0.154, 0.234, 1.084",\
"0.158, 0.237, 1.084");
}
fall_transition(CELL_TABLE) {
values("0.277, 0.36, 1.499",\
"0.277, 0.362, 1.499",\
"0.278, 0.37, 1.5");
values("0.276, 0.356, 1.5",\
"0.277, 0.357, 1.5",\
"0.278, 0.363, 1.5");
}
}
}
@@ -170,9 +170,9 @@ cell (sram_2_16_1_scn3me_subm){
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
@@ -204,9 +204,9 @@ cell (sram_2_16_1_scn3me_subm){
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
@@ -237,9 +237,9 @@ cell (sram_2_16_1_scn3me_subm){
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
@@ -270,9 +270,9 @@ cell (sram_2_16_1_scn3me_subm){
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
@@ -298,19 +298,19 @@ cell (sram_2_16_1_scn3me_subm){
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("4.39065104738");
values("4.42361814306");
}
fall_power(scalar){
values("4.39065104738");
values("4.42361814306");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("5.00353945572");
values("4.97118480973");
}
fall_power(scalar){
values("5.00353945572");
values("4.97118480973");
}
}
internal_power(){