mirror of https://github.com/VLSIDA/OpenRAM.git
Added fix for column mux lib generation.:
This commit is contained in:
parent
4a8ec7a687
commit
b5ca417b26
|
|
@ -319,7 +319,7 @@ class spice():
|
||||||
corner_slew = SLEW_APPROXIMATION*corner_delay
|
corner_slew = SLEW_APPROXIMATION*corner_delay
|
||||||
return delay_data(corner_delay, corner_slew)
|
return delay_data(corner_delay, corner_slew)
|
||||||
|
|
||||||
def get_stage_effort(self, corner, slew, load=0.0):
|
def get_stage_effort(self, cout, inp_is_rise=True):
|
||||||
"""Inform users undefined delay module while building new modules"""
|
"""Inform users undefined delay module while building new modules"""
|
||||||
debug.warning("Design Class {0} logical effort function needs to be defined"
|
debug.warning("Design Class {0} logical effort function needs to be defined"
|
||||||
.format(self.__class__.__name__))
|
.format(self.__class__.__name__))
|
||||||
|
|
|
||||||
|
|
@ -1285,7 +1285,7 @@ class delay(simulation):
|
||||||
debug.warning("Analytical characterization results are not supported for multiport.")
|
debug.warning("Analytical characterization results are not supported for multiport.")
|
||||||
|
|
||||||
# Probe set to 0th bit, does not matter for analytical delay.
|
# Probe set to 0th bit, does not matter for analytical delay.
|
||||||
self.set_probe('0', 0)
|
self.set_probe('0'*self.addr_size, 0)
|
||||||
self.create_graph()
|
self.create_graph()
|
||||||
self.set_internal_spice_names()
|
self.set_internal_spice_names()
|
||||||
self.create_measurement_names()
|
self.create_measurement_names()
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue