From b5ca417b26324dffddf47e4d4f7b7dc96ab124b2 Mon Sep 17 00:00:00 2001 From: jsowash Date: Tue, 3 Sep 2019 11:50:39 -0700 Subject: [PATCH] Added fix for column mux lib generation.: --- compiler/base/hierarchy_spice.py | 6 +++--- compiler/characterizer/delay.py | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 5166ac6b..e189c183 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -319,13 +319,13 @@ class spice(): corner_slew = SLEW_APPROXIMATION*corner_delay return delay_data(corner_delay, corner_slew) - def get_stage_effort(self, corner, slew, load=0.0): + def get_stage_effort(self, cout, inp_is_rise=True): """Inform users undefined delay module while building new modules""" debug.warning("Design Class {0} logical effort function needs to be defined" .format(self.__class__.__name__)) debug.warning("Class {0} name {1}" - .format(self.__class__.__name__, - self.name)) + .format(self.__class__.__name__, + self.name)) return None def get_cin(self): diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 7a905b11..b05c022e 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -1050,7 +1050,7 @@ class delay(simulation): def get_address_row_number(self, probe_address): """Calculates wordline row number of data bit under test using address and column mux size""" - + return int(probe_address[self.sram.col_addr_size:],2) def prepare_netlist(self): @@ -1285,7 +1285,7 @@ class delay(simulation): debug.warning("Analytical characterization results are not supported for multiport.") # Probe set to 0th bit, does not matter for analytical delay. - self.set_probe('0', 0) + self.set_probe('0'*self.addr_size, 0) self.create_graph() self.set_internal_spice_names() self.create_measurement_names()