Enable pruning by default (except on unit tests)

compiler/options.py

@@ -102,7 +102,7 @@ class options(optparse.Values):
     # This determines whether LVS and DRC is checked for every submodule.
     inline_lvsdrc = False
     # Remove noncritical memory cells for characterization speed-up
-    trim_netlist = False
+    trim_netlist = True
     # Run with extracted parasitics
     use_pex = False
     # Output config with all options

compiler/tests/22_psram_1bank_2mux_func_test.py

@@ -23,7 +23,8 @@ class psram_1bank_2mux_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
-
+        OPTS.trim_netlist = False
+        
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"
         OPTS.dummy_bitcell="dummy_pbitcell"

compiler/tests/22_psram_1bank_4mux_func_test.py

@@ -24,7 +24,8 @@ class psram_1bank_4mux_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
-
+        OPTS.trim_netlist = False
+        
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"
         OPTS.dummy_bitcell="dummy_pbitcell"

compiler/tests/22_psram_1bank_8mux_func_test.py

@@ -24,7 +24,8 @@ class psram_1bank_8mux_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
-
+        OPTS.trim_netlist = False
+        
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"
         OPTS.dummy_bitcell="dummy_pbitcell"

compiler/tests/22_psram_1bank_nomux_func_test.py

@@ -23,7 +23,8 @@ class psram_1bank_nomux_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
-
+        OPTS.trim_netlist = False
+        
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"
         OPTS.dummy_bitcell="dummy_pbitcell"

compiler/tests/22_sram_1bank_2mux_func_test.py

@@ -24,7 +24,8 @@ class sram_1bank_2mux_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
-
+        OPTS.trim_netlist = False
+        
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
         import characterizer

compiler/tests/22_sram_1bank_2mux_global_func_test.py

@@ -24,7 +24,8 @@ class sram_1bank_2mux_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
-
+        OPTS.trim_netlist = False
+        
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
         import characterizer

compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py

@@ -24,6 +24,7 @@ class sram_1bank_2mux_sparecols_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload

compiler/tests/22_sram_1bank_4mux_func_test.py

@@ -24,7 +24,8 @@ class sram_1bank_4mux_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
-
+        OPTS.trim_netlist = False
+        
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
         import characterizer

compiler/tests/22_sram_1bank_8mux_func_test.py

@@ -24,7 +24,8 @@ class sram_1bank_8mux_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
-
+        OPTS.trim_netlist = False
+        
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
         import characterizer

compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py

@@ -23,6 +23,8 @@ class psram_1bank_nomux_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1

compiler/tests/22_sram_1bank_nomux_func_test.py

@@ -24,6 +24,7 @@ class sram_1bank_nomux_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload

compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py

@@ -24,6 +24,7 @@ class sram_1bank_nomux_sparecols_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload

compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py

@@ -23,6 +23,8 @@ class sram_wmask_1w_1r_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1

compiler/tests/22_sram_wmask_func_test.py

@@ -24,6 +24,7 @@ class sram_wmask_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload