mirror of https://github.com/VLSIDA/OpenRAM.git
Updated leakage power golden data in hspice delay test.
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@ -72,16 +72,16 @@ class timing_sram_test(openram_test):
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'write0_power': [0.34616749999999996],
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'write0_power': [0.34616749999999996],
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'write1_power': [0.2792924]}
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'write1_power': [0.2792924]}
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elif OPTS.tech_name == "scn4m_subm":
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl': [1.7445000000000002],
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golden_data = {'delay_hl': [1.7448],
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'delay_lh': [1.7445000000000002],
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'delay_lh': [1.7448],
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'leakage_power': 0.025635599999999998,
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'leakage_power': 0.0006356744000000001,
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'min_period': 6.25,
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'min_period': 6.25,
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'read0_power': [13.58],
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'read0_power': [12.9846],
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'read1_power': [12.9926],
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'read1_power': [12.9722],
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'slew_hl': [1.7434000000000003],
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'slew_hl': [1.7433],
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'slew_lh': [1.7434000000000003],
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'slew_lh': [1.7433],
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'write0_power': [14.9158],
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'write0_power': [14.8772],
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'write1_power': [11.9173]}
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'write1_power': [11.7217]}
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else:
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else:
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self.assertTrue(False) # other techs fail
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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# Check if no too many or too few results
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