diff --git a/compiler/bitcells/bitcell_2port.py b/compiler/bitcells/bitcell_2port.py
index fcba7a38..75d654c0 100644
--- a/compiler/bitcells/bitcell_2port.py
+++ b/compiler/bitcells/bitcell_2port.py
@@ -99,3 +99,8 @@ class bitcell_2port(bitcell_base.bitcell_base):
         # Port 1 edges
         graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
         graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)
+
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+        
+        return False
\ No newline at end of file
diff --git a/compiler/bitcells/replica_bitcell_2port.py b/compiler/bitcells/replica_bitcell_2port.py
index f75d514f..8d113805 100644
--- a/compiler/bitcells/replica_bitcell_2port.py
+++ b/compiler/bitcells/replica_bitcell_2port.py
@@ -49,3 +49,8 @@ class replica_bitcell_2port(bitcell_base.bitcell_base):
         # Port 1 edges
         graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
         graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)
+
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+        
+        return False
\ No newline at end of file