diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py
index 94e7b396..cfeb4ab2 100755
--- a/compiler/tests/01_library_drc_test.py
+++ b/compiler/tests/01_library_drc_test.py
@@ -17,7 +17,7 @@ import debug
 class library_drc_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import verify
 
diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py
index 2916a3da..5f53753b 100755
--- a/compiler/tests/02_library_lvs_test.py
+++ b/compiler/tests/02_library_lvs_test.py
@@ -17,7 +17,7 @@ import debug
 class library_lvs_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import verify
 
diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py
index e43eeee3..2e3f4f0f 100755
--- a/compiler/tests/03_contact_test.py
+++ b/compiler/tests/03_contact_test.py
@@ -18,7 +18,7 @@ import debug
 class contact_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         for layer_stack in [("metal1", "via1", "metal2"), ("poly", "contact", "metal1")]:
diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py
index 4cc1f942..be210c8f 100755
--- a/compiler/tests/03_path_test.py
+++ b/compiler/tests/03_path_test.py
@@ -17,7 +17,7 @@ import debug
 class path_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import wire_path
         import tech
diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py
index 81977458..ae323d90 100755
--- a/compiler/tests/03_ptx_1finger_nmos_test.py
+++ b/compiler/tests/03_ptx_1finger_nmos_test.py
@@ -18,7 +18,7 @@ import debug
 class ptx_1finger_nmos_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import tech
 
diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py
index bb995099..3bf3e293 100755
--- a/compiler/tests/03_ptx_1finger_pmos_test.py
+++ b/compiler/tests/03_ptx_1finger_pmos_test.py
@@ -18,7 +18,7 @@ import debug
 class ptx_1finger_pmos_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import tech
 
diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py
index bbfea153..95700e8f 100755
--- a/compiler/tests/03_ptx_3finger_nmos_test.py
+++ b/compiler/tests/03_ptx_3finger_nmos_test.py
@@ -18,7 +18,7 @@ import debug
 class ptx_3finger_nmos_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import tech
 
diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py
index 88b80321..8c09cf9b 100755
--- a/compiler/tests/03_ptx_3finger_pmos_test.py
+++ b/compiler/tests/03_ptx_3finger_pmos_test.py
@@ -18,7 +18,7 @@ import debug
 class ptx_3finger_pmos_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import tech
 
diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py
index 52d8f2f2..da9e438d 100755
--- a/compiler/tests/03_ptx_4finger_nmos_test.py
+++ b/compiler/tests/03_ptx_4finger_nmos_test.py
@@ -18,7 +18,7 @@ import debug
 class ptx_4finger_nmos_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import tech
 
diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py
index 3cdcc492..4fc60d5c 100755
--- a/compiler/tests/03_ptx_4finger_pmos_test.py
+++ b/compiler/tests/03_ptx_4finger_pmos_test.py
@@ -18,7 +18,7 @@ import debug
 class ptx_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import tech
 
diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py
index 0cd977f6..2e2db319 100755
--- a/compiler/tests/03_wire_test.py
+++ b/compiler/tests/03_wire_test.py
@@ -17,7 +17,7 @@ import debug
 class wire_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import wire
         import tech
diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py
index a19145f5..b39e48ea 100755
--- a/compiler/tests/04_dummy_pbitcell_test.py
+++ b/compiler/tests/04_dummy_pbitcell_test.py
@@ -18,7 +18,7 @@ import debug
 class replica_pbitcell_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import dummy_pbitcell
         
diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py
index 7cb21615..f7e5f304 100755
--- a/compiler/tests/04_pand2_test.py
+++ b/compiler/tests/04_pand2_test.py
@@ -18,7 +18,7 @@ import debug
 class pand2_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         global verify
         import verify
diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py
index 2efbdacf..e58f1ee9 100755
--- a/compiler/tests/04_pand3_test.py
+++ b/compiler/tests/04_pand3_test.py
@@ -18,7 +18,7 @@ import debug
 class pand3_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         global verify
         import verify
diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py
index e6b093b9..450c0263 100755
--- a/compiler/tests/04_pbitcell_test.py
+++ b/compiler/tests/04_pbitcell_test.py
@@ -19,7 +19,7 @@ from sram_factory import factory
 class pbitcell_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         OPTS.num_rw_ports=1
diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py
index 847a2139..ffd06962 100755
--- a/compiler/tests/04_pbuf_test.py
+++ b/compiler/tests/04_pbuf_test.py
@@ -18,7 +18,7 @@ import debug
 class pbuf_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py
index 95865f84..e65b6fad 100755
--- a/compiler/tests/04_pdriver_test.py
+++ b/compiler/tests/04_pdriver_test.py
@@ -18,7 +18,7 @@ import debug
 class pdriver_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py
index 22da05db..ae3f480b 100755
--- a/compiler/tests/04_pinv_10x_test.py
+++ b/compiler/tests/04_pinv_10x_test.py
@@ -18,7 +18,7 @@ import debug
 class pinv_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Checking 8x inverter")
diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py
index fe91d339..0b8c055a 100755
--- a/compiler/tests/04_pinv_1x_beta_test.py
+++ b/compiler/tests/04_pinv_1x_beta_test.py
@@ -18,7 +18,7 @@ import debug
 class pinv_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Checking 1x beta=3 size inverter")
diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py
index d25192f5..e6c0bff2 100755
--- a/compiler/tests/04_pinv_1x_test.py
+++ b/compiler/tests/04_pinv_1x_test.py
@@ -18,7 +18,7 @@ import debug
 class pinv_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Checking 1x size inverter")
diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py
index b4419bc5..0a0e63ec 100755
--- a/compiler/tests/04_pinv_2x_test.py
+++ b/compiler/tests/04_pinv_2x_test.py
@@ -18,7 +18,7 @@ import debug
 class pinv_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Checking 2x size inverter")
diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py
index 0a32c7c4..df7645d1 100755
--- a/compiler/tests/04_pinvbuf_test.py
+++ b/compiler/tests/04_pinvbuf_test.py
@@ -18,7 +18,7 @@ import debug
 class pinvbuf_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py
index 0f0f2a5d..f939738a 100755
--- a/compiler/tests/04_pnand2_test.py
+++ b/compiler/tests/04_pnand2_test.py
@@ -18,7 +18,7 @@ import debug
 class pnand2_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Checking 2-input nand gate")
diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py
index be1ac294..f1af19ac 100755
--- a/compiler/tests/04_pnand3_test.py
+++ b/compiler/tests/04_pnand3_test.py
@@ -18,7 +18,7 @@ import debug
 class pnand3_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Checking 3-input nand gate")
diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py
index 046fc6ab..ea0d6dbc 100755
--- a/compiler/tests/04_pnor2_test.py
+++ b/compiler/tests/04_pnor2_test.py
@@ -18,7 +18,7 @@ import debug
 class pnor2_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Checking 2-input nor gate")
diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py
index 3b0d2e0c..1c12ad8b 100755
--- a/compiler/tests/04_precharge_test.py
+++ b/compiler/tests/04_precharge_test.py
@@ -18,7 +18,7 @@ import debug
 class precharge_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         
         # check precharge in single port
diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py
index 1e075629..77336c61 100755
--- a/compiler/tests/04_replica_pbitcell_test.py
+++ b/compiler/tests/04_replica_pbitcell_test.py
@@ -18,7 +18,7 @@ import debug
 class replica_pbitcell_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import replica_pbitcell
         
diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py
index 07dada90..de5870fc 100755
--- a/compiler/tests/04_single_level_column_mux_test.py
+++ b/compiler/tests/04_single_level_column_mux_test.py
@@ -20,7 +20,7 @@ import debug
 class single_level_column_mux_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         
         # check single level column mux in single port
diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py
index 6e757067..3426f0c5 100755
--- a/compiler/tests/05_bitcell_1rw_1r_array_test.py
+++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py
@@ -20,7 +20,7 @@ import debug
 class bitcell_1rw_1r_array_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         
         OPTS.bitcell = "bitcell_1rw_1r"
diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py
index f9bebaef..256ad526 100755
--- a/compiler/tests/05_bitcell_array_test.py
+++ b/compiler/tests/05_bitcell_array_test.py
@@ -20,7 +20,7 @@ import debug
 class array_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing 4x4 array for 6t_cell")
diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py
index a10ee83d..97ec8db5 100755
--- a/compiler/tests/05_dummy_array_test.py
+++ b/compiler/tests/05_dummy_array_test.py
@@ -16,7 +16,7 @@ import debug
 class dummy_row_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing dummy row for 6t_cell")
diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py
index 0e58da3a..6c5e4729 100755
--- a/compiler/tests/05_pbitcell_array_test.py
+++ b/compiler/tests/05_pbitcell_array_test.py
@@ -19,7 +19,7 @@ import debug
 class pbitcell_array_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
diff --git a/compiler/tests/05_replica_pbitcell_array_test.py b/compiler/tests/05_replica_pbitcell_array_test.py
index 13204f0a..34bdbee7 100755
--- a/compiler/tests/05_replica_pbitcell_array_test.py
+++ b/compiler/tests/05_replica_pbitcell_array_test.py
@@ -16,7 +16,7 @@ import debug
 class replica_bitcell_array_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py
index 01d9c0e7..9d8353f3 100755
--- a/compiler/tests/06_hierarchical_decoder_test.py
+++ b/compiler/tests/06_hierarchical_decoder_test.py
@@ -18,7 +18,7 @@ import debug
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         # Doesn't require hierarchical decoder
         # debug.info(1, "Testing 4 row sample for hierarchical_decoder")
diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py
index ddc9cec2..2e55f5e9 100755
--- a/compiler/tests/06_hierarchical_predecode2x4_test.py
+++ b/compiler/tests/06_hierarchical_predecode2x4_test.py
@@ -18,7 +18,7 @@ import debug
 class hierarchical_predecode2x4_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         # checking hierarchical precode 2x4 for single port
diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py
index 4e4c5b9a..da7573e1 100755
--- a/compiler/tests/06_hierarchical_predecode3x8_test.py
+++ b/compiler/tests/06_hierarchical_predecode3x8_test.py
@@ -18,7 +18,7 @@ import debug
 class hierarchical_predecode3x8_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         # checking hierarchical precode 3x8 for single port
diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py
index 09eeb98c..ff6c51eb 100755
--- a/compiler/tests/07_single_level_column_mux_array_test.py
+++ b/compiler/tests/07_single_level_column_mux_array_test.py
@@ -17,7 +17,7 @@ import debug
 class single_level_column_mux_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import single_level_column_mux_array
         
diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py
index 5340404b..d4f5591b 100755
--- a/compiler/tests/08_precharge_array_test.py
+++ b/compiler/tests/08_precharge_array_test.py
@@ -18,7 +18,7 @@ import debug
 class precharge_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         # check precharge array in single port
diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py
index 873833bd..f64503f8 100755
--- a/compiler/tests/08_wordline_driver_test.py
+++ b/compiler/tests/08_wordline_driver_test.py
@@ -20,7 +20,7 @@ import debug
 class wordline_driver_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         # check wordline driver for single port
diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py
index ad9cfeb2..3baf51f0 100755
--- a/compiler/tests/09_sense_amp_array_test.py
+++ b/compiler/tests/09_sense_amp_array_test.py
@@ -18,7 +18,7 @@ import debug
 class sense_amp_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         # check sense amp array for single port
diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py
index ad3826a2..16e280ed 100755
--- a/compiler/tests/10_write_driver_array_test.py
+++ b/compiler/tests/10_write_driver_array_test.py
@@ -18,7 +18,7 @@ import debug
 class write_driver_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         # check write driver array for single port
diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py
index f61aa144..743d331a 100755
--- a/compiler/tests/10_write_driver_array_wmask_test.py
+++ b/compiler/tests/10_write_driver_array_wmask_test.py
@@ -20,7 +20,7 @@ import debug
 class write_driver_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         # check write driver array for single port
diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py
index eb7e3ad9..303ce2f4 100755
--- a/compiler/tests/10_write_mask_and_array_test.py
+++ b/compiler/tests/10_write_mask_and_array_test.py
@@ -20,7 +20,7 @@ import debug
 class write_mask_and_array_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         # check write driver array for single port
diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py
index eff032a4..9d8798c5 100755
--- a/compiler/tests/11_dff_array_test.py
+++ b/compiler/tests/11_dff_array_test.py
@@ -18,7 +18,7 @@ import debug
 class dff_array_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing dff_array for 3x3")
diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py
index 18344676..6eb338a5 100755
--- a/compiler/tests/11_dff_buf_array_test.py
+++ b/compiler/tests/11_dff_buf_array_test.py
@@ -18,7 +18,7 @@ import debug
 class dff_buf_array_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing dff_buf_array for 3x3")
diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py
index 1183a4ea..070cdb56 100755
--- a/compiler/tests/11_dff_buf_test.py
+++ b/compiler/tests/11_dff_buf_test.py
@@ -18,7 +18,7 @@ import debug
 class dff_buf_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing dff_buf 4x 8x")
diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py
index 7ff58be4..813feda0 100755
--- a/compiler/tests/12_tri_gate_array_test.py
+++ b/compiler/tests/12_tri_gate_array_test.py
@@ -18,7 +18,7 @@ import debug
 class tri_gate_array_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(1, "Testing tri_gate_array for columns=8, word_size=8")
diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py
index 989fab48..4b893a8a 100755
--- a/compiler/tests/13_delay_chain_test.py
+++ b/compiler/tests/13_delay_chain_test.py
@@ -18,7 +18,7 @@ import debug
 class delay_chain_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing delay_chain")
diff --git a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py
index 579b2805..9fbdf497 100755
--- a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py
+++ b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py
@@ -16,7 +16,7 @@ import debug
 class replica_bitcell_array_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         OPTS.bitcell = "bitcell_1rw_1r"
diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py
index 0514d0ce..19413cd5 100755
--- a/compiler/tests/14_replica_bitcell_array_test.py
+++ b/compiler/tests/14_replica_bitcell_array_test.py
@@ -16,7 +16,7 @@ import debug
 class replica_bitcell_array_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing 4x4 array for 6t_cell")
diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py
index 9deadc41..57c92e84 100755
--- a/compiler/tests/14_replica_column_test.py
+++ b/compiler/tests/14_replica_column_test.py
@@ -16,7 +16,7 @@ import debug
 class replica_column_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(2, "Testing replica column for 6t_cell")
diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py
index e81391f2..919e2335 100755
--- a/compiler/tests/16_control_logic_multiport_test.py
+++ b/compiler/tests/16_control_logic_multiport_test.py
@@ -22,7 +22,7 @@ import debug
 class control_logic_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import control_logic
         import tech
diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py
index 677cd271..ecc6008a 100755
--- a/compiler/tests/16_control_logic_test.py
+++ b/compiler/tests/16_control_logic_test.py
@@ -18,7 +18,7 @@ import debug
 class control_logic_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import control_logic
         import tech
diff --git a/compiler/tests/18_port_address_test.py b/compiler/tests/18_port_address_test.py
index 0ebb3508..23f35540 100755
--- a/compiler/tests/18_port_address_test.py
+++ b/compiler/tests/18_port_address_test.py
@@ -16,7 +16,7 @@ import debug
 class port_address_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(1, "Port address 16 rows")
diff --git a/compiler/tests/18_port_data_test.py b/compiler/tests/18_port_data_test.py
index 4939ad33..71681056 100755
--- a/compiler/tests/18_port_data_test.py
+++ b/compiler/tests/18_port_data_test.py
@@ -16,7 +16,7 @@ import debug
 class port_data_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py
index d486a7fd..f670990e 100755
--- a/compiler/tests/18_port_data_wmask_test.py
+++ b/compiler/tests/18_port_data_wmask_test.py
@@ -18,7 +18,7 @@ import debug
 class port_data_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py
index 27a9a279..adb2523e 100755
--- a/compiler/tests/19_bank_select_test.py
+++ b/compiler/tests/19_bank_select_test.py
@@ -18,7 +18,7 @@ import debug
 class bank_select_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(1, "No column mux, rw control logic")
diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py
index c7293126..f4c622c7 100755
--- a/compiler/tests/19_multi_bank_test.py
+++ b/compiler/tests/19_multi_bank_test.py
@@ -19,7 +19,7 @@ import debug
 class multi_bank_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py
index aa7c5992..7c3da444 100755
--- a/compiler/tests/19_pmulti_bank_test.py
+++ b/compiler/tests/19_pmulti_bank_test.py
@@ -19,7 +19,7 @@ import debug
 class multi_bank_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py
index d64a5edd..8c6ddb12 100755
--- a/compiler/tests/19_psingle_bank_test.py
+++ b/compiler/tests/19_psingle_bank_test.py
@@ -19,7 +19,7 @@ import debug
 class psingle_bank_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         
diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py
index bc9f8ff0..b3e18407 100755
--- a/compiler/tests/19_single_bank_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_1rw_1r_test.py
@@ -18,7 +18,7 @@ import debug
 class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py
index 4170e66a..c1228e5a 100755
--- a/compiler/tests/19_single_bank_1w_1r_test.py
+++ b/compiler/tests/19_single_bank_1w_1r_test.py
@@ -18,7 +18,7 @@ import debug
 class single_bank_1w_1r_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py
index 53e32b65..6cff481b 100755
--- a/compiler/tests/19_single_bank_test.py
+++ b/compiler/tests/19_single_bank_test.py
@@ -18,7 +18,7 @@ import debug
 class single_bank_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py
index 0d70c43e..50567ebb 100755
--- a/compiler/tests/19_single_bank_wmask_test.py
+++ b/compiler/tests/19_single_bank_wmask_test.py
@@ -18,7 +18,7 @@ import debug
 class single_bank_wmask_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
index eb885f0b..599cb2ce 100755
--- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
@@ -19,7 +19,7 @@ import debug
 class psram_1bank_2mux_1rw_1w_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
index ab475aaf..0d236bc2 100755
--- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
@@ -21,7 +21,7 @@ import debug
 class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
index 154fda4e..30b951fb 100755
--- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
@@ -19,7 +19,7 @@ import debug
 class psram_1bank_2mux_1w_1r_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py
index b0dec84b..44272b2d 100755
--- a/compiler/tests/20_psram_1bank_2mux_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_test.py
@@ -19,7 +19,7 @@ import debug
 class psram_1bank_2mux_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
index 8d4d048f..472a60a6 100755
--- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
+++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
@@ -18,7 +18,7 @@ import debug
 class psram_1bank_4mux_1rw_1r_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
index 5824c60a..a8d635ba 100755
--- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
@@ -18,7 +18,7 @@ import debug
 class sram_1bank_2mux_1rw_1r_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         
diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
index 6cfac474..bf572700 100755
--- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
@@ -19,7 +19,7 @@ import debug
 class psram_1bank_2mux_1w_1r_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         
diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py
index e2d431bf..582f5217 100755
--- a/compiler/tests/20_sram_1bank_2mux_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_test.py
@@ -19,7 +19,7 @@ import debug
 class sram_1bank_2mux_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         c = sram_config(word_size=4,
diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py
index dba51753..50bd41dc 100755
--- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py
@@ -21,7 +21,7 @@ import debug
 class sram_1bank_2mux_wmask_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         c = sram_config(word_size=8,
diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py
index 823b841a..05cb7c0d 100755
--- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py
+++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py
@@ -21,7 +21,7 @@ import debug
 class sram_1bank_32b_1024_wmask_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         c = sram_config(word_size=32,
diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py
index 7a77650e..e38ef7c4 100755
--- a/compiler/tests/20_sram_1bank_4mux_test.py
+++ b/compiler/tests/20_sram_1bank_4mux_test.py
@@ -19,7 +19,7 @@ import debug
 class sram_1bank_4mux_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         c = sram_config(word_size=4,
diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
index ae75618f..69a623d2 100755
--- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
@@ -18,7 +18,7 @@ import debug
 class sram_1bank_8mux_1rw_1r_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
 
diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py
index d7ae16a8..dfdcd5b7 100755
--- a/compiler/tests/20_sram_1bank_8mux_test.py
+++ b/compiler/tests/20_sram_1bank_8mux_test.py
@@ -19,7 +19,7 @@ import debug
 class sram_1bank_8mux_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         c = sram_config(word_size=2,
diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
index ecc44117..f9b96b84 100755
--- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
@@ -18,7 +18,7 @@ import debug
 class sram_1bank_nomux_1rw_1r_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         
diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py
index c21e6694..c79d8552 100755
--- a/compiler/tests/20_sram_1bank_nomux_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_test.py
@@ -19,7 +19,7 @@ import debug
 class sram_1bank_nomux_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         c = sram_config(word_size=4,
diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py
index 71d97db2..24d7c97d 100755
--- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py
@@ -21,7 +21,7 @@ import debug
 class sram_1bank_nomux_wmask_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         c = sram_config(word_size=8,
diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py
index b1d54460..5fd4bf29 100755
--- a/compiler/tests/20_sram_2bank_test.py
+++ b/compiler/tests/20_sram_2bank_test.py
@@ -19,7 +19,7 @@ import debug
 class sram_2bank_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
         c = sram_config(word_size=16,
diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py
index c27ab122..832a6308 100755
--- a/compiler/tests/21_hspice_delay_test.py
+++ b/compiler/tests/21_hspice_delay_test.py
@@ -18,7 +18,7 @@ import debug
 class timing_sram_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py
index fb81d137..1844fd39 100755
--- a/compiler/tests/21_hspice_setuphold_test.py
+++ b/compiler/tests/21_hspice_setuphold_test.py
@@ -18,7 +18,7 @@ import debug
 class timing_setup_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py
index 289af76e..e21d658e 100755
--- a/compiler/tests/21_model_delay_test.py
+++ b/compiler/tests/21_model_delay_test.py
@@ -20,7 +20,7 @@ class model_delay_test(openram_test):
     """ Compare the accuracy of the analytical model with a spice simulation. """
     
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py
index 86cbc518..fb72a57d 100755
--- a/compiler/tests/21_ngspice_delay_test.py
+++ b/compiler/tests/21_ngspice_delay_test.py
@@ -18,7 +18,7 @@ import debug
 class timing_sram_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py
index 37fb56c0..246bdff9 100755
--- a/compiler/tests/21_ngspice_setuphold_test.py
+++ b/compiler/tests/21_ngspice_setuphold_test.py
@@ -18,7 +18,7 @@ import debug
 class timing_setup_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py
index ae9de4f6..7a6da149 100755
--- a/compiler/tests/22_psram_1bank_2mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_2mux_func_test.py
@@ -18,7 +18,7 @@ import debug
 class psram_1bank_2mux_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py
index 7d945951..facd3874 100755
--- a/compiler/tests/22_psram_1bank_4mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_4mux_func_test.py
@@ -19,7 +19,7 @@ import debug
 class psram_1bank_4mux_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py
index 3173210d..acf0c3a4 100755
--- a/compiler/tests/22_psram_1bank_8mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_8mux_func_test.py
@@ -19,7 +19,7 @@ import debug
 class psram_1bank_8mux_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py
index ed7f17fc..b7d6cf78 100755
--- a/compiler/tests/22_psram_1bank_nomux_func_test.py
+++ b/compiler/tests/22_psram_1bank_nomux_func_test.py
@@ -19,7 +19,7 @@ import debug
 class psram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py
index 04856d3a..10d19c1c 100755
--- a/compiler/tests/22_sram_1bank_2mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_2mux_func_test.py
@@ -19,7 +19,7 @@ import debug
 class sram_1bank_2mux_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py
index a92ef19e..d2bf7886 100755
--- a/compiler/tests/22_sram_1bank_4mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_4mux_func_test.py
@@ -19,7 +19,7 @@ import debug
 class sram_1bank_4mux_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py
index 538c72e6..3f6ff55f 100755
--- a/compiler/tests/22_sram_1bank_8mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_8mux_func_test.py
@@ -19,7 +19,7 @@ import debug
 class sram_1bank_8mux_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py
index 5a8e5697..2aa20e99 100755
--- a/compiler/tests/22_sram_1bank_nomux_func_test.py
+++ b/compiler/tests/22_sram_1bank_nomux_func_test.py
@@ -19,7 +19,7 @@ import debug
 class sram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py
index 370a4de8..d271d1e5 100755
--- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py
+++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py
@@ -19,7 +19,7 @@ import debug
 class psram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/22_sram_wmask_1w_1r_func_test.py b/compiler/tests/22_sram_wmask_1w_1r_func_test.py
index 7111299f..50acd5bf 100755
--- a/compiler/tests/22_sram_wmask_1w_1r_func_test.py
+++ b/compiler/tests/22_sram_wmask_1w_1r_func_test.py
@@ -21,7 +21,7 @@ import debug
 class sram_wmask_1w_1r_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py
index 22c4b29b..d29795a9 100755
--- a/compiler/tests/22_sram_wmask_func_test.py
+++ b/compiler/tests/22_sram_wmask_func_test.py
@@ -19,7 +19,7 @@ import debug
 class sram_wmask_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py
index 7527fd2b..1e853fae 100755
--- a/compiler/tests/23_lib_sram_model_corners_test.py
+++ b/compiler/tests/23_lib_sram_model_corners_test.py
@@ -18,7 +18,7 @@ import debug
 class lib_model_corners_lib_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.netlist_only = True
 
diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py
index dab05941..6043d83f 100755
--- a/compiler/tests/23_lib_sram_model_test.py
+++ b/compiler/tests/23_lib_sram_model_test.py
@@ -18,7 +18,7 @@ import debug
 class lib_sram_model_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.netlist_only = True
         
diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py
index 4c9b17ba..9df647ce 100755
--- a/compiler/tests/23_lib_sram_prune_test.py
+++ b/compiler/tests/23_lib_sram_prune_test.py
@@ -18,7 +18,7 @@ import debug
 class lib_sram_prune_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.trim_netlist = True
diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py
index 4c5d4ed8..08bb5565 100755
--- a/compiler/tests/23_lib_sram_test.py
+++ b/compiler/tests/23_lib_sram_test.py
@@ -17,7 +17,7 @@ import debug
 class lib_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.trim_netlist = False
diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py
index bb0a5116..14ad551f 100755
--- a/compiler/tests/24_lef_sram_test.py
+++ b/compiler/tests/24_lef_sram_test.py
@@ -18,7 +18,7 @@ import debug
 class lef_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         from sram import sram
diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py
index ce058f4a..c385e455 100755
--- a/compiler/tests/25_verilog_sram_test.py
+++ b/compiler/tests/25_verilog_sram_test.py
@@ -17,7 +17,7 @@ import debug
 class verilog_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         from sram import sram
diff --git a/compiler/tests/26_hspice_pex_pinv_test.py b/compiler/tests/26_hspice_pex_pinv_test.py
index da52e8c3..b4b55cdb 100755
--- a/compiler/tests/26_hspice_pex_pinv_test.py
+++ b/compiler/tests/26_hspice_pex_pinv_test.py
@@ -20,7 +20,7 @@ import debug
 class hspice_pex_pinv_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import pinv
 
diff --git a/compiler/tests/26_ngspice_pex_pinv_test.py b/compiler/tests/26_ngspice_pex_pinv_test.py
index c1cf97bd..e6e0cfb2 100755
--- a/compiler/tests/26_ngspice_pex_pinv_test.py
+++ b/compiler/tests/26_ngspice_pex_pinv_test.py
@@ -19,7 +19,7 @@ import debug
 
 class ngspice_pex_pinv_test(openram_test):
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import pinv
 
diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py
index bc445a68..4eff7db5 100755
--- a/compiler/tests/26_pex_test.py
+++ b/compiler/tests/26_pex_test.py
@@ -19,7 +19,7 @@ import debug
 class sram_func_test(openram_test):
 
     def runTest(self):
-        config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         OPTS.use_pex = True
diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py
index 0c7d5e17..b3c35010 100755
--- a/compiler/tests/30_openram_back_end_test.py
+++ b/compiler/tests/30_openram_back_end_test.py
@@ -20,7 +20,7 @@ class openram_back_end_test(openram_test):
 
     def runTest(self):
         OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
-        config_file = "{}/tests/{}/config_back_end".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config_back_end".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(1, "Testing top-level back-end openram.py with 2-bit, 16 word SRAM.")
diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py
index 79b19dc6..8ed76627 100755
--- a/compiler/tests/30_openram_front_end_test.py
+++ b/compiler/tests/30_openram_front_end_test.py
@@ -20,7 +20,7 @@ class openram_front_end_test(openram_test):
 
     def runTest(self):
         OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
-        config_file = "{}/tests/{}/config_front_end".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+        config_file = "{}/tests/configs/config_front_end".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         debug.info(1, "Testing top-level front-end openram.py with 2-bit, 16 word SRAM.")
diff --git a/compiler/tests/scn4m_subm/config.py b/compiler/tests/configs/config.py
similarity index 90%
rename from compiler/tests/scn4m_subm/config.py
rename to compiler/tests/configs/config.py
index abb31435..b43d2707 100644
--- a/compiler/tests/scn4m_subm/config.py
+++ b/compiler/tests/configs/config.py
@@ -5,10 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from globals import OPTS
 word_size = 1
 num_words = 16
 
-tech_name = "scn4m_subm"
+tech_name = OPTS.tech_name
 process_corners = ["TT"]
 supply_voltages = [5.0]
 temperatures = [25]
diff --git a/compiler/tests/scn4m_subm/config_back_end.py b/compiler/tests/configs/config_back_end.py
similarity index 90%
rename from compiler/tests/scn4m_subm/config_back_end.py
rename to compiler/tests/configs/config_back_end.py
index 35e4cd91..3ef6fae1 100644
--- a/compiler/tests/scn4m_subm/config_back_end.py
+++ b/compiler/tests/configs/config_back_end.py
@@ -5,10 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from globals import OPTS
 word_size = 1
 num_words = 16
 
-tech_name = "scn4m_subm"
+tech_name = OPTS.tech_name
 process_corners = ["TT"]
 supply_voltages = [5.0]
 temperatures = [25]
diff --git a/compiler/tests/scn4m_subm/config_front_end.py b/compiler/tests/configs/config_front_end.py
similarity index 89%
rename from compiler/tests/scn4m_subm/config_front_end.py
rename to compiler/tests/configs/config_front_end.py
index 142191a0..18bb1b3e 100644
--- a/compiler/tests/scn4m_subm/config_front_end.py
+++ b/compiler/tests/configs/config_front_end.py
@@ -5,10 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from globals import OPTS
 word_size = 1
 num_words = 16
 
-tech_name = "scn4m_subm"
+tech_name = OPTS.tech_name
 process_corners = ["TT"]
 supply_voltages = [5.0]
 temperatures = [25]
diff --git a/compiler/tests/freepdk45/config.py b/compiler/tests/freepdk45/config.py
deleted file mode 100644
index 3103217f..00000000
--- a/compiler/tests/freepdk45/config.py
+++ /dev/null
@@ -1,18 +0,0 @@
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
-# All rights reserved.
-#
-word_size = 1
-num_words = 16
-
-tech_name = "freepdk45"
-process_corners = ["TT"]
-supply_voltages = [1.0]
-temperatures = [25]
-
-route_supplies = True
-check_lvsdrc = True
-
diff --git a/compiler/tests/freepdk45/config_back_end.py b/compiler/tests/freepdk45/config_back_end.py
deleted file mode 100644
index 68417a3b..00000000
--- a/compiler/tests/freepdk45/config_back_end.py
+++ /dev/null
@@ -1,20 +0,0 @@
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
-# All rights reserved.
-#
-word_size = 1
-num_words = 16
-
-tech_name = "freepdk45"
-process_corners = ["TT"]
-supply_voltages = [1.0]
-temperatures = [25]
-
-inline_lvsdrc = True
-route_supplies = True
-check_lvsdrc = True
-analytical_delay = False
-
diff --git a/compiler/tests/freepdk45/config_front_end.py b/compiler/tests/freepdk45/config_front_end.py
deleted file mode 100644
index 1886d808..00000000
--- a/compiler/tests/freepdk45/config_front_end.py
+++ /dev/null
@@ -1,18 +0,0 @@
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
-# All rights reserved.
-#
-word_size = 1
-num_words = 16
-
-tech_name = "freepdk45"
-process_corners = ["TT"]
-supply_voltages = [1.0]
-temperatures = [25]
-
-analytical_delay = False
-
-