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https://github.com/VLSIDA/OpenRAM.git
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Hard cells can accept height parameter too.
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@@ -57,21 +57,15 @@ class hierarchical_decoder(design.design):
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self.DRC_LVS()
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def add_modules(self):
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if OPTS.tech_name == "s8":
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self.and2 = factory.create(module_type="pand2_dec")
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else:
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self.and2 = factory.create(module_type="pand2_dec",
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height=self.cell_height)
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self.and2 = factory.create(module_type="and2_dec",
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height=self.cell_height)
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self.add_mod(self.and2)
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if OPTS.tech_name == "s8":
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self.and3 = factory.create(module_type="pand3_dec")
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else:
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self.and3 = factory.create(module_type="pand3_dec",
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height=self.cell_height)
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self.and3 = factory.create(module_type="and3_dec",
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height=self.cell_height)
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self.add_mod(self.and3)
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# TBD
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# self.and4 = factory.create(module_type="pand4_dec")
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# self.and4 = factory.create(module_type="and4_dec")
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# self.add_mod(self.and4)
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self.add_decoders()
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@@ -180,6 +174,7 @@ class hierarchical_decoder(design.design):
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# Two extra pitches between modules on left and right
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self.internal_routing_width = self.total_number_of_predecoder_outputs * self.bus_pitch + self.bus_pitch
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self.row_decoder_height = self.and2.height * self.num_outputs
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# Extra bus space for supply contacts
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self.input_routing_width = self.num_inputs * self.bus_pitch + self.bus_space
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@@ -42,13 +42,13 @@ class hierarchical_predecode(design.design):
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# FIXME: Default parms are required for hard cells for now.
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if self.number_of_inputs == 2:
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self.and_mod = factory.create(module_type="pand2_dec",
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self.and_mod = factory.create(module_type="and2_dec",
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height=self.cell_height)
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elif self.number_of_inputs == 3:
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self.and_mod = factory.create(module_type="pand3_dec",
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self.and_mod = factory.create(module_type="and3_dec",
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height=self.cell_height)
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elif self.number_of_inputs == 4:
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self.and_mod = factory.create(module_type="pand4_dec",
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self.and_mod = factory.create(module_type="and4_dec",
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height=self.cell_height)
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else:
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debug.error("Invalid number of predecode inputs: {}".format(self.number_of_inputs), -1)
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