mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 09:30:38 +02:00
updated imports to match upstream dev openram
This commit is contained in:
@@ -1,8 +1,8 @@
|
||||
|
||||
|
||||
from base import design
|
||||
from base import vector
|
||||
from sram_factory import factory
|
||||
from openram.base import design
|
||||
from openram.base import vector
|
||||
from openram.sram_factory import factory
|
||||
|
||||
class rom_array_gnd_tap(design):
|
||||
|
||||
|
||||
@@ -9,11 +9,10 @@
|
||||
|
||||
import math
|
||||
from .bitcell_base_array import bitcell_base_array
|
||||
from base import vector
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import tech
|
||||
from tech import drc
|
||||
from openram.base import vector
|
||||
from openram import OPTS
|
||||
from openram.sram_factory import factory
|
||||
from openram.tech import drc
|
||||
|
||||
class rom_base_array(bitcell_base_array):
|
||||
|
||||
|
||||
@@ -1,11 +1,11 @@
|
||||
|
||||
import math
|
||||
from base import vector
|
||||
from base import design
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
from openram.base import vector
|
||||
from openram.base import design
|
||||
from openram import OPTS
|
||||
from openram.sram_factory import factory
|
||||
import tech
|
||||
from tech import drc
|
||||
from openram.tech import drc
|
||||
|
||||
class rom_base_bank(design):
|
||||
|
||||
|
||||
@@ -7,11 +7,10 @@
|
||||
#
|
||||
|
||||
from .rom_dummy_cell import rom_dummy_cell
|
||||
from base import vector
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
|
||||
from tech import drc
|
||||
from openram.base import vector
|
||||
from openram import OPTS
|
||||
from openram.sram_factory import factory
|
||||
from openram.tech import drc
|
||||
|
||||
|
||||
class rom_base_cell(rom_dummy_cell):
|
||||
|
||||
@@ -6,13 +6,12 @@
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
import math
|
||||
from base import design
|
||||
from sram_factory import factory
|
||||
from base import vector
|
||||
from globals import OPTS
|
||||
import tech
|
||||
from tech import drc
|
||||
from math import ceil, log
|
||||
from openram.base import design
|
||||
from openram.sram_factory import factory
|
||||
from openram.base import vector
|
||||
from openram import OPTS
|
||||
from openram.tech import drc
|
||||
|
||||
|
||||
class rom_decoder(design):
|
||||
@@ -23,7 +22,7 @@ class rom_decoder(design):
|
||||
# array gets rotated 90deg so that rows/cols switch
|
||||
self.strap_spacing=strap_spacing
|
||||
self.num_outputs = num_outputs
|
||||
self.num_inputs = math.ceil(math.log(num_outputs, 2))
|
||||
self.num_inputs = ceil(log(num_outputs, 2))
|
||||
self.create_decode_map()
|
||||
|
||||
for i in range(2 * self.num_inputs): print(self.decode_map[i])
|
||||
|
||||
@@ -8,11 +8,11 @@
|
||||
|
||||
|
||||
|
||||
from base import design
|
||||
from base import vector
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
from tech import drc
|
||||
from openram.base import design
|
||||
from openram.base import vector
|
||||
from openram import OPTS
|
||||
from openram.sram_factory import factory
|
||||
from openram.tech import drc
|
||||
|
||||
|
||||
class rom_dummy_cell(design):
|
||||
|
||||
@@ -6,10 +6,10 @@
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
from base import design
|
||||
from sram_factory import factory
|
||||
from base import vector
|
||||
from tech import layer, drc
|
||||
from openram.base import design
|
||||
from openram.sram_factory import factory
|
||||
from openram.base import vector
|
||||
from openram.tech import layer, drc
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,9 +1,15 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
|
||||
from base import design
|
||||
from base import vector
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
from openram.base import design
|
||||
from openram.base import vector
|
||||
from openram import OPTS
|
||||
from openram.sram_factory import factory
|
||||
|
||||
class rom_poly_tap(design):
|
||||
|
||||
|
||||
@@ -6,12 +6,12 @@
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
import math
|
||||
from base import geometry
|
||||
from base import design
|
||||
from sram_factory import factory
|
||||
from base import vector
|
||||
from tech import layer, drc
|
||||
from math import ceil
|
||||
from openram.base import geometry
|
||||
from openram.base import design
|
||||
from openram.sram_factory import factory
|
||||
from openram.base import vector
|
||||
from openram.tech import layer, drc
|
||||
|
||||
|
||||
|
||||
@@ -40,7 +40,7 @@ class rom_precharge_array(design):
|
||||
|
||||
|
||||
if strap_spacing != 0:
|
||||
self.num_straps = math.ceil(self.cols / self.strap_spacing)
|
||||
self.num_straps = ceil(self.cols / self.strap_spacing)
|
||||
self.array_col_size = self.cols + self.num_straps
|
||||
else:
|
||||
self.num_straps = 0
|
||||
|
||||
@@ -6,12 +6,12 @@
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
from base import design
|
||||
from base import vector
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
from openram.base import design
|
||||
from openram.base import vector
|
||||
from openram import OPTS
|
||||
from openram.sram_factory import factory
|
||||
|
||||
from tech import drc
|
||||
from openram.tech import drc
|
||||
|
||||
|
||||
class rom_precharge_cell(design):
|
||||
|
||||
Reference in New Issue
Block a user