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update to sense amp and write driver modules

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This commit is contained in:
Joey Kunzler
2020-03-30 20:00:32 -07:00
parent 9907daaffa
commit b0d2946c80
3 changed files with 33 additions and 28 deletions
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compiler/modules/sense_amp_array.py
+17 -16
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@@ -22,7 +22,7 @@ class sense_amp_array(design.design):
def __init__(self, name, word_size, words_per_row):
design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name))
self.add_comment("word_size {0}".format(word_size))
self.add_comment("word_size {0}".format(word_size))
self.add_comment("words_per_row: {0}".format(words_per_row))
self.word_size = word_size
@@ -56,7 +56,7 @@ class sense_amp_array(design.design):
def create_layout(self):
self.height = self.amp.height
if self.bitcell.width > self.amp.width:
self.width = self.bitcell.width * self.word_size * self.words_per_row
else:
@@ -76,16 +76,16 @@ class sense_amp_array(design.design):
self.add_pin(self.en_name, "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_modules(self):
self.amp = factory.create(module_type="sense_amp")
self.add_mod(self.amp)
# This is just used for measurements,
# so don't add the module
self.bitcell = factory.create(module_type="bitcell")
def create_sense_amp_array(self):
self.local_insts = []
for i in range(0,self.word_size):
@@ -121,11 +121,11 @@ class sense_amp_array(design.design):
amp_position = vector(xoffset, 0)
self.local_insts[i].place(offset=amp_position,mirror=mirror)
def add_layout_pins(self):
for i in range(len(self.local_insts)):
inst = self.local_insts[i]
self.add_power_pin(name = "gnd",
loc = inst.get_pin("gnd").center(),
start_layer="m2",
@@ -141,40 +141,41 @@ class sense_amp_array(design.design):
dout_pin = inst.get_pin(inst.mod.dout_name)
self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
layer="m2",
layer=bl_pin.layer,
offset=bl_pin.ll(),
width=bl_pin.width(),
height=bl_pin.height())
self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
layer="m2",
layer=br_pin.layer,
offset=br_pin.ll(),
width=br_pin.width(),
height=br_pin.height())
self.add_layout_pin(text=self.data_name + "_{0}".format(i),
layer="m2",
layer=dout_pin.layer,
offset=dout_pin.ll(),
width=dout_pin.width(),
height=dout_pin.height())
def route_rails(self):
# add sclk rail across entire array
sclk = self.amp.get_pin(self.amp.en_name)
sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1)
self.add_layout_pin(text=self.en_name,
layer="m1",
layer=sclk.layer,
offset=sclk_offset,
width=self.width,
height=drc("minwidth_m1"))
height=drc("minwidth_" + sclk.layer))
def input_load(self):
return self.amp.input_load()
def get_en_cin(self):
"""Get the relative capacitance of all the sense amp enable connections in the array"""
sense_amp_en_cin = self.amp.get_en_cin()
return sense_amp_en_cin * self.word_size
def get_drain_cin(self):
"""Get the relative capacitance of the drain of the PMOS isolation TX"""
from tech import parameter