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Fix indent bug that failed to create rbl wl pin labels.

This commit is contained in:
mrg 2020-10-08 15:28:01 -07:00
parent 01fe02bd90
commit b0b15e8151
1 changed files with 33 additions and 40 deletions
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7
compiler/modules/replica_bitcell_array.py
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@ -267,16 +267,9 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
for port in self.all_ports:
for bit in self.all_ports:
#if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
if bit != port:
self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
#else:
# self.rbl_wordline_names[port].append("rbl_wl0_{0}_{1}".format(port, bit))
# self.rbl_wordline_names[port].append("rbl_wl1_{0}_{1}".format(port, bit))
# if bit != port:
# self.gnd_wordline_names.append("rbl0_wl_{0}_{1}".format(port, bit))
# self.gnd_wordline_names.append("rbl1_wl_{0}_{1}".format(port, bit))
self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]