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Missing output via in control logic

This commit is contained in:
mrg 2020-06-30 16:23:07 -07:00
parent 3379f46da1
commit b07f30cb9e
1 changed files with 8 additions and 4 deletions
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10
compiler/modules/control_logic.py
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@ -797,10 +797,14 @@ class control_logic(design.design):
out_pin = inst.get_pin(pin_name)
right_pos = out_pin.center() + vector(self.width - out_pin.cx(), 0)
self.add_layout_pin_segment_center(text=out_name,
self.add_path(out_pin.layer, [out_pin.center(), right_pos])
self.add_via_stack_center(from_layer=out_pin.layer,
to_layer="m1",
offset=right_pos)
self.add_layout_pin_rect_center(text=out_name,
layer="m1",
start=out_pin.center(),
end=right_pos)
offset=right_pos)
def route_supply(self):
""" Add vdd and gnd to the instance cells """