diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index 74fad6a5..78215d49 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -797,10 +797,14 @@ class control_logic(design.design):
         
         out_pin = inst.get_pin(pin_name)
         right_pos = out_pin.center() + vector(self.width - out_pin.cx(), 0)
-        self.add_layout_pin_segment_center(text=out_name,
-                                           layer="m1",
-                                           start=out_pin.center(),
-                                           end=right_pos)
+        
+        self.add_path(out_pin.layer, [out_pin.center(), right_pos])
+        self.add_via_stack_center(from_layer=out_pin.layer,
+                                  to_layer="m1",
+                                  offset=right_pos)
+        self.add_layout_pin_rect_center(text=out_name,
+                                        layer="m1",
+                                        offset=right_pos)
 
     def route_supply(self):
         """ Add vdd and gnd to the instance cells """