diff --git a/technology/scn3me_subm/tech/calibreDRC_scn3me_subm.rul b/technology/scn3me_subm/tech/calibreDRC_scn3me_subm.rul
new file mode 100755
index 00000000..91d35fb4
--- /dev/null
+++ b/technology/scn3me_subm/tech/calibreDRC_scn3me_subm.rul
@@ -0,0 +1,225 @@
+////////////////////////////////////////////////////////////
+// DEFINE BOOLEAN LAYERS
+////////////////////////////////////////////////////////////
+LAYOUT USE DATABASE PRECISION YES
+
+layer pwell              41
+layer nwell              42
+layer active             43
+layer poly               46
+layer nimplant           45
+layer pimplant           44
+layer contact            25
+layer active_contact     48
+layer poly_contact       47
+layer metal1             49
+layer via1               50
+layer metal2             51
+layer via2               61
+layer metal3             62
+layer glass              52
+layer pad                26
+
+//Enabling incremental connectivity for antenna rule checks
+DRC Incremental Connect Yes
+
+well = nwell OR pwell
+gate = poly AND active
+implant = nimplant OR pimplant
+fieldpoly = poly NOT active
+
+contactenc1 = active OR poly
+contactenc = contactenc1 AND metal1
+diode = contact AND active
+act_poly = interact poly active
+
+GROUP mask_check
+//Well.2 Well.4 
+Poly.1 Poly.2 Poly.3 Poly.4 Poly.5 
+Active.1 Active.2 // Active.3  
+Contact.1 Contact.2 Contact.3 Contact.4
+Contact.5 Contact.6 Metal1.1 Metal1.2 Metal1.3 
+
+
+
+//Well.1 {
+//@Nwell and Pwell must not overlap
+//AND nwell pwell
+//}
+
+//Well.2 {
+//@Min spacing of pwell to nwell = 0.00  
+//EXTERNAL nwell pwell < 0.00    
+//}
+
+//Well.4 {
+//@Min width of nwell = 3.6      
+//INTERNAL nwell < 3.6       
+//}
+
+Poly.1 {
+@Min width of poly = 0.6    
+INTERNAL poly < 0.6        
+}
+
+Poly.2 {
+@Min spacing of gate poly = 0.9    
+EXTERNAL gate < 0.9
+}
+
+Poly.3 {
+@Min extension of poly past active = 0.6  
+ENCLOSURE active poly < 0.6     
+}
+
+Poly.4 {
+@Minimum active enclosure of gate =0.6     
+ENCLOSURE poly active < 0.6         
+}
+
+Poly.5 {
+@Minimum spacing of poly to active = 0.3    
+EXTERNAL act_poly active < 0.3      
+}
+
+Active.1 {
+@Minimum width of active = 0.9
+INTERNAL active < 0.9
+}
+
+Active.2 {
+@Minimum spacing of active areas =  0.9
+EXTERNAL active < 0.9
+}
+
+//Active.3 {
+//@Minimum well enclosure of active = 1.8
+//ENCLOSURE active well < 1.8
+//}
+
+Contact.1 {
+@Minimum width of contact = 0.6                 
+INTERNAL contact < 0.6                    
+}
+
+Contact.2 {
+@Minimum spacing of contact = 0.9         
+EXTERNAL contact < 0.9                    
+}
+
+Contact.3 {
+@Contact must be inside metal1 and active or poly
+NOT contact contactenc
+}
+
+Contact.4 {
+@Minimum active enclosure of contact = 0.3       
+ENCLOSURE contact active < 0.3                    
+}
+
+Contact.5 {
+@Minimum poly enclosure of contact = 0.3          
+ENCLOSURE contact poly < 0.3                      
+}
+
+Contact.6 {
+@Minimum spacing of contact to poly = 0.6         
+EXTERNAL poly contact < 0.6                     
+}
+
+Metal1.1 {
+@Minimum width of metal1 = 0.9                   
+INTERNAL metal1 < 0.9                           
+}
+
+Metal1.2 {
+@Minimum spacing of metal1 = 0.9                
+EXTERNAL metal1 < 0.9                           
+}
+
+Metal1.3 {
+@Metal1 must extend past contact by 0.3 on two opposite sides     
+RECTANGLE ENCLOSURE contact metal1
+GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE
+}
+
+Metal1.4 {
+@Metal1 must extend past via1 by 0.3 on two opposite sides       
+RECTANGLE ENCLOSURE via1 metal1
+GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE
+}
+
+Via1.1 {
+@Minimum width of via1 = 0.6           
+INTERNAL via1 < 0.6                   
+}
+
+Via1.2 {
+@Minimum spacing of via1 = 0.6       
+EXTERNAL via1 < 0.6                 
+}
+
+Via1.3 {
+@Via1 must be inside metal1
+NOT via1 metal1
+}
+
+
+Metal2.1 {
+@Minimum width of metal2 = 0.9
+INTERNAL metal2 < 0.9
+}
+
+Metal2.2 {
+@Minimum spacing of metal2 = 0.9  
+EXTERNAL metal2 < 0.9             
+}
+
+Metal2.3 {
+@Metal2 must extend past via1 by 0.3 on two opposite sides          
+RECTANGLE ENCLOSURE via1 metal2
+GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE                       
+}
+
+Metal2.4 {
+@Metal2 must extend past via2 by 0.3 on two opposite sides          
+RECTANGLE ENCLOSURE via2 metal2
+GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE                          
+}
+
+Via2.1 {
+@Minimum width of via2 = 0.6     
+INTERNAL via2 < 0.6             
+}
+
+Via2.2 {
+@Minimum spacing of via2 = 0.9            
+EXTERNAL via2 < 0.9                     
+}
+
+Via2.3 {
+@Via2 must be inside metal2
+NOT via2 metal2
+}
+
+Via2.4 {
+@Via2 must be inside metal3
+NOT via2 metal3
+}
+
+Metal3.1 {
+@Minimum width of metal3 = 1.5             
+INTERNAL metal3 < 1.5                      
+}
+
+Metal3.2 {
+@Minimum spacing of metal3 = 0.9           
+EXTERNAL metal3 < 0.9                      
+}
+
+Metal3.3 {
+@Metal3 must extend past via2 by 0.6 on two opposite sides               
+RECTANGLE ENCLOSURE via2 metal3
+GOOD 0.00 0.6 OPPOSITE 0.00 0.6 OPPOSITE            
+}
+
diff --git a/technology/scn3me_subm/tech/calibreLVS_scn3me_subm.rul b/technology/scn3me_subm/tech/calibreLVS_scn3me_subm.rul
new file mode 100755
index 00000000..5d3516a6
--- /dev/null
+++ b/technology/scn3me_subm/tech/calibreLVS_scn3me_subm.rul
@@ -0,0 +1,123 @@
+TITLE   "LVS Rule File for scn3me_subm"
+
+LVS POWER NAME vdd
+LVS GROUND NAME gnd GROUND
+LVS REDUCE PARALLEL MOS yes
+LVS REDUCE SERIES MOS yes
+LVS REDUCE SEMI SERIES MOS yes
+LVS FILTER UNUSED MOS no
+LVS RECOGNIZE GATES all
+LVS COMPONENT TYPE PROPERTY element
+LVS COMPONENT SUBTYPE PROPERTY model
+LVS IGNORE PORTS no
+
+LVS REPORT mask.lvs.rep
+LVS REPORT OPTION N
+LVS REPORT MAXIMUM 50
+MASK RESULTS DATABASE maskdb
+
+precision 1000
+resolution 250
+
+TEXT LAYER metal1 metal2 metal3
+PORT LAYER TEXT  metal1 metal2 metal3 
+
+
+layer pwell              41
+layer nwell              42
+layer active             43
+layer poly               46
+layer nimplant           45
+layer pimplant           44
+layer contact            25
+layer active_contact     48
+layer poly_contact       47
+layer metal1             49
+layer via1               50
+layer metal2             51
+layer via2               61
+layer metal3             62
+layer glass              52
+layer pad                26
+
+connect metal1 metal2 by via1
+connect metal2 metal3 by via2
+
+pdif = active and pimplant     // P-diffusion
+ndif = active and nimplant     // N-diffusion
+
+ngate = poly and ndif          // N-Transistor
+pgate = poly and pdif          // P-transistor
+
+nsrcdrn = ndif not ngate       // N-tansistor Source and Drain contacts diffusion region
+psrcdrn = pdif not pgate       // P-tansistor Source and Drain contacts diffusion region
+
+pcont = psrcdrn and pwell
+
+ntapcont = active not interact pimplant
+ptapcont = active not interact nimplant
+
+bulk = extent
+nsub = (bulk not pwell) and nwell
+ncont = nsrcdrn and nsub
+
+connect metal1 poly psrcdrn nsrcdrn by contact mask
+connect psrcdrn pwell by pcont mask
+connect nsrcdrn nsub by ncont mask
+
+ncont1= ntapcont and nsub
+pcont1= ptapcont and pwell
+connect metal1 ncont1 by contact mask
+connect metal1 pcont1 by contact mask
+connect ncont1 nsub
+connect pcont1 pwell
+
+connect psrcdrn metal1 by contact 
+connect nsrcdrn metal1 by contact
+
+connect psrcdrn metal1 by active_contact 
+connect nsrcdrn metal1 by active_contact
+
+connect poly metal1 by contact
+
+connect poly metal1 by poly_contact
+
+device mp (p) pgate poly (G) psrcdrn (S) psrcdrn (D) nsub  CMACRO FET_PROPERTIES pgate nsub
+device mn (n) ngate poly (G) nsrcdrn (S) nsrcdrn (D) pwell  CMACRO FET_PROPERTIES ngate pwell
+
+VARIABLE trace_delta 4e-9
+
+DMACRO FET_TRACE device_type device_name {
+TRACE PROPERTY device_type(device_name) l l trace_delta ABSOLUTE
+TRACE PROPERTY device_type(device_name) w w trace_delta ABSOLUTE
+
+}
+
+CMACRO FET_TRACE MN n 
+CMACRO FET_TRACE MP p
+
+DMACRO FET_PROPERTIES seed well{
+[
+PROPERTY  W, L, AS, AD, PS, PD
+
+      AS = area(S)
+      AD = area(D)
+      PS = perimeter(S)
+      PD = perimeter(D)
+      if ( AS == 0 ) {
+         AD = area(D) / 2
+         AS = AD
+         PD = perimeter(D) / 2
+         PS = PD
+         }
+      if ( AD == 0 ) {
+         AS = area(S) / 2
+         AD = AS
+         PS = perimeter(S) / 2
+         PD = PS
+         }
+     W = (perim_co(seed,S) + perim_co(seed,D) ) * 0.5
+     L = (perim(seed) - perim_co(seed,S) - perim_in(seed,S) - perim_co(seed,D) - perim_in(seed,D) ) * 0.5
+   
+]
+}