mirror of https://github.com/VLSIDA/OpenRAM.git
lvs fix for regression tests
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218a553ac5
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@ -114,7 +114,6 @@ class replica_column(design.design):
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mod=self.dummy_cell)
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mod=self.dummy_cell)
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self.connect_inst(self.get_bitcell_pins(0, row))
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self.connect_inst(self.get_bitcell_pins(0, row))
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def place_instances(self):
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def place_instances(self):
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from tech import cell_properties
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from tech import cell_properties
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# Flip the mirrors if we have an odd number of replica+dummy rows at the bottom
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# Flip the mirrors if we have an odd number of replica+dummy rows at the bottom
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@ -149,20 +148,30 @@ class replica_column(design.design):
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self.cell_inst[row].place(offset=offset,
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self.cell_inst[row].place(offset=offset,
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mirror=dir_key)
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mirror=dir_key)
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def add_layout_pins(self):
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def add_layout_pins(self):
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""" Add the layout pins """
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""" Add the layout pins """
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for bl_name in self.cell.get_all_bitline_names():
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for bl_name in self.cell.get_all_bitline_names():
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bl_pin = self.cell_inst[1].get_pin(bl_name)
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bl_pin = self.cell_inst[0].get_pin(bl_name)
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self.add_layout_pin(text=bl_name,
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self.add_layout_pin(text=bl_name,
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layer=bl_pin.layer,
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layer=bl_pin.layer,
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offset=bl_pin.ll(),
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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width=bl_pin.width(),
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height=self.height)
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height=self.height)
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for row in range(1, self.total_size - 1):
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try:
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end_caps_enabled = cell_properties.bitcell.end_caps
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except AttributeError:
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end_caps_enabled = False
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if end_caps_enabled:
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row_range_max = self.total_size - 1
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row_range_min = 1
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else:
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row_range_max = self.total_size
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row_range_min = 0
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for row in range(row_range_min, row_range_max):
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for wl_name in self.cell.get_all_wl_names():
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for wl_name in self.cell.get_all_wl_names():
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wl_pin = self.cell_inst[row].get_pin(wl_name)
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wl_pin = self.cell_inst[row].get_pin(wl_name)
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self.add_layout_pin(text="{0}_{1}".format(wl_name,row),
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self.add_layout_pin(text="{0}_{1}".format(wl_name,row),
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@ -172,7 +181,7 @@ class replica_column(design.design):
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height=wl_pin.height())
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height=wl_pin.height())
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# For every second row and column, add a via for gnd and vdd
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# For every second row and column, add a via for gnd and vdd
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for row in range(1, self.total_size - 1):
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for row in range(row_range_min, row_range_max):
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inst = self.cell_inst[row]
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inst = self.cell_inst[row]
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for pin_name in ["vdd", "gnd"]:
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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self.copy_layout_pin(inst, pin_name)
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