mirror of https://github.com/VLSIDA/OpenRAM.git
Add new supplies to RBL and control logic
This commit is contained in:
Matt Guthaus
parent
93e830e800
commit
afcc3563ae
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@ -97,7 +97,9 @@ class control_logic(design.design):
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self.internal_list = ["clk_buf", "clk_buf_bar", "we", "cs", "oe"]
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self.internal_width = len(self.internal_list)*self.m2_pitch
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# Ooutputs to the bank
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self.output_list = ["s_en", "w_en", "tri_en", "tri_en_bar", "clk_buf_bar", "clk_buf"]
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self.output_list = ["s_en", "w_en", "clk_buf_bar", "clk_buf"]
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# # with tri/tri_en
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# self.output_list = ["s_en", "w_en", "tri_en", "tri_en_bar", "clk_buf_bar", "clk_buf"]
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self.supply_list = ["vdd", "gnd"]
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self.rail_width = len(self.input_list)*len(self.output_list)*self.m2_pitch
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self.rail_x_offsets = {}
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@ -107,7 +109,9 @@ class control_logic(design.design):
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def add_rails(self):
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""" Add the input signal inverted tracks """
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height = 6*self.inv1.height - self.m2_pitch
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height = 4*self.inv1.height - self.m2_pitch
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# with tri/tri_en
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#height = 6*self.inv1.height - self.m2_pitch
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for i in range(len(self.internal_list)):
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name = self.internal_list[i]
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offset = vector(i*self.m2_pitch + self.ctrl_dff_array.width, 0)
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@ -122,22 +126,28 @@ class control_logic(design.design):
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def add_modules(self):
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""" Place all the modules """
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# Keep track of the right end of the rows for max width
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self.row_ends = []
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self.add_dffs()
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self.add_clk_buffer(row=0)
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self.add_clk_row(row=0)
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self.add_we_row(row=2)
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self.add_trien_row(row=3)
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self.add_trien_bar_row(row=4)
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self.add_rblk_row(row=5)
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self.add_sen_row(row=6)
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self.add_rbl(row=7)
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# self.add_trien_row(row=3)
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# self.add_trien_bar_row(row=4)
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self.add_rblk_row(row=3)
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self.add_sen_row(row=4)
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self.add_rbl(row=5)
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self.add_lvs_correspondence_points()
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# This offset is used for placement of the control logic in
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# the SRAM level.
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self.control_logic_center = vector(self.ctrl_dff_array.width, self.replica_bitline_offset.y)
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self.height = self.rbl_inst.uy()
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# Find max of logic rows
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max_row = max(self.row_rblk_end_x, self.row_trien_end_x, self.row_trien_bar_end_x,
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self.row_sen_end_x, self.row_we_end_x, self.row_we_end_x)
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max_row = max(self.row_ends)
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# Max of modules or logic rows
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self.width = max(self.clkbuf.rx(), self.rbl_inst.rx(), max_row)
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@ -146,8 +156,8 @@ class control_logic(design.design):
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def add_routing(self):
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""" Routing between modules """
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self.route_dffs()
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self.route_trien()
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self.route_trien_bar()
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#self.route_trien()
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#self.route_trien_bar()
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self.route_rblk()
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self.route_wen()
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self.route_sen()
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@ -158,7 +168,7 @@ class control_logic(design.design):
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def add_rbl(self,row):
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""" Add the replica bitline """
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y_off = row * self.inv1.height + 2*self.m1_pitch
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# Add the RBL above the rows
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# Add to the right of the control rows and routing channel
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self.replica_bitline_offset = vector(0, y_off)
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@ -168,7 +178,7 @@ class control_logic(design.design):
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self.connect_inst(["rblk", "pre_s_en", "vdd", "gnd"])
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def add_clk_buffer(self,row):
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def add_clk_row(self,row):
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""" Add the multistage clock buffer below the control flops """
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x_off = self.ctrl_dff_array.width + self.internal_width
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y_off = row*self.inv1.height
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@ -184,7 +194,10 @@ class control_logic(design.design):
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offset=clkbuf_offset)
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self.connect_inst(["clk","clk_buf_bar","clk_buf","vdd","gnd"])
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# This clock buffer is two rows high
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self.row_ends.append(x_off)
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self.row_ends.append(x_off)
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def add_rblk_row(self,row):
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@ -215,7 +228,7 @@ class control_logic(design.design):
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self.connect_inst(["rblk_bar", "rblk", "vdd", "gnd"])
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x_off += self.inv1.width
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self.row_rblk_end_x = x_off
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self.row_ends.append(x_off)
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def add_sen_row(self,row):
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""" The sense enable buffer gets placed to the far right of the
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@ -245,7 +258,7 @@ class control_logic(design.design):
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mirror=mirror)
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self.connect_inst(["pre_s_en", "pre_s_en_bar", "vdd", "gnd"])
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self.row_sen_end_x = self.replica_bitline.width
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self.row_ends.append(x_off)
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def add_trien_row(self, row):
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x_off = self.ctrl_dff_array.width + self.internal_width
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@ -288,7 +301,7 @@ class control_logic(design.design):
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self.row_trien_end_x = x_off
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self.row_ends.append(x_off)
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def add_trien_bar_row(self, row):
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@ -331,7 +344,7 @@ class control_logic(design.design):
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self.row_trien_bar_end_x = x_off
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self.row_ends.append(x_off)
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def route_dffs(self):
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""" Route the input inverters """
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@ -408,7 +421,7 @@ class control_logic(design.design):
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self.connect_inst(["pre_w_en_bar", "w_en", "vdd", "gnd"])
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x_off += self.inv8.width
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self.row_we_end_x = x_off
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self.row_ends.append(x_off)
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def route_rblk(self):
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@ -436,7 +449,6 @@ class control_logic(design.design):
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offset=rblk_pos,
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rotate=90)
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def connect_rail_from_right(self,inst, pin, rail):
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""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
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@ -581,35 +593,31 @@ class control_logic(design.design):
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def route_supply(self):
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""" Route the vdd and gnd for the rows of logic. """
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rows_start = 0
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rows_end = self.width
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#well_width = drc["minwidth_well"]
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for i in range(8):
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# Route all of the rows that were created
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for i in range(len(self.row_ends) + 1):
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if i%2:
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name = "vdd"
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well_type = "nwell"
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else:
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name = "gnd"
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well_type = "pwell"
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yoffset = i*self.inv1.height
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self.add_layout_pin_segment_center(text=name,
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layer="metal1",
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start=vector(rows_start,yoffset),
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end=vector(rows_end,yoffset))
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row_start = vector(rows_start,yoffset)
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row_end = vector(rows_end,yoffset)
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self.add_segment_center(layer="metal1",
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start=row_start,
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end=row_end)
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self.add_power_pin(name, row_start)
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self.add_power_pin(name, row_end)
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# # also add a well +- around the rail
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# well_offset = vector(rows_start,yoffset-0.5*well_width)
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# self.add_rect(layer=well_type,
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# offset=well_offset,
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# width=rows_end-rows_start,
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# height=well_width)
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# self.add_rect(layer="vtg",
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# offset=well_offset,
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# width=rows_end-rows_start,
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# height=well_width)
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self.copy_layout_pin(self.rbl_inst,"gnd")
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@ -57,15 +57,18 @@ class replica_bitline(design.design):
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# away from the delay chain/inverter with space for three M2 tracks
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self.bitcell_offset = vector(0,self.replica_bitcell.height)
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self.rbl_offset = self.bitcell_offset
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# Gap between the delay chain and RBL
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gap_width = 2*self.m2_pitch
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# Quadrant 4: with some space below it and tracks on the right for vdd/gnd
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self.delay_chain_offset = vector(-self.delay_chain.width-4*self.m2_pitch,self.replica_bitcell.height)
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self.delay_chain_offset = vector(-self.delay_chain.width-gap_width,self.replica_bitcell.height)
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# Will be flipped vertically below the delay chain
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self.rbl_inv_offset = self.delay_chain_offset + vector(0.5*self.delay_chain.width, 0)
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# Placed next to the replica bitcell
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self.access_tx_offset = vector(-4*self.m2_pitch-self.access_tx.width-self.inv.width, 0.5*self.inv.height)
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self.access_tx_offset = vector(-gap_width-self.access_tx.width-self.inv.width, 0.5*self.inv.height)
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