From af3102750490eecc691b58bc853bcbd0422f4714 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 21 Jun 2021 13:13:53 -0700 Subject: [PATCH] Fix error in 1 spare column Verilog --- compiler/base/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 3da3b9aa..205baeb7 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -230,7 +230,7 @@ class verilog: if self.num_spare_cols == 1: self.vf.write(" if (spare_wen{0}_reg)\n".format(port)) - self.vf.write(" mem[addr{0}_reg][{1}] = din{0}_reg[{1}];\n".format(port, self.word_size + num)) + self.vf.write(" mem[addr{0}_reg][{1}] = din{0}_reg[{1}];\n".format(port, self.word_size)) else: for num in range(self.num_spare_cols): self.vf.write(" if (spare_wen{0}_reg[{1}])\n".format(port, num))