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passing code style

This commit is contained in:
Jacob Walker 2023-02-28 21:10:52 -08:00
parent 79efff9ca6
commit af0209ec96
16 changed files with 170 additions and 174 deletions
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5
compiler/modules/rom_address_control_buf.py
View File

@ -130,8 +130,6 @@ class rom_address_control_buf(design):
self.add_via_stack_center(from_layer=self.inv_layer, to_layer=self.route_layer, offset=self.addr_bar_nand.get_pin("A").center()) self.add_via_stack_center(from_layer=self.inv_layer, to_layer=self.route_layer, offset=self.addr_bar_nand.get_pin("A").center())
self.add_segment_center(self.route_layer, clk_offset, vector(clk_offset.x, clk2_pin.cy())) self.add_segment_center(self.route_layer, clk_offset, vector(clk_offset.x, clk2_pin.cy()))
# Route first NAND output to second NAND input # Route first NAND output to second NAND input
start = A_out.center() start = A_out.center()
end = Aint_in.center() end = Aint_in.center()
@ -139,18 +137,15 @@ class rom_address_control_buf(design):
self.add_via_stack_center(Aint_in.center(), self.inv_layer, "m2") self.add_via_stack_center(Aint_in.center(), self.inv_layer, "m2")
self.add_via_stack_center(A_out.center(), self.inv_layer, "m2") self.add_via_stack_center(A_out.center(), self.inv_layer, "m2")
# Route first NAND to output pin # Route first NAND to output pin
self.add_segment_center("m2", end, vector(end.x, self.addr_bar_nand.uy())) self.add_segment_center("m2", end, vector(end.x, self.addr_bar_nand.uy()))
self.add_layout_pin_rect_center("A_out", offset=vector(end.x, self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2") self.add_layout_pin_rect_center("A_out", offset=vector(end.x, self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2")
# Route second NAND to output pin # Route second NAND to output pin
self.add_via_stack_center(Abar_out.center(), self.inv_layer, "m2") self.add_via_stack_center(Abar_out.center(), self.inv_layer, "m2")
self.add_segment_center("m2", Abar_out.center(), vector(Abar_out.cx(), self.addr_bar_nand.uy())) self.add_segment_center("m2", Abar_out.center(), vector(Abar_out.cx(), self.addr_bar_nand.uy()))
self.add_layout_pin_rect_center("Abar_out", offset=vector(Abar_out.cx(), self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2") self.add_layout_pin_rect_center("Abar_out", offset=vector(Abar_out.cx(), self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2")
# Route inverter output to NAND # Route inverter output to NAND
end = vector(Abar_int_out.cx(), Abar_in.cy() + 0.5 * self.interconnect_width) end = vector(Abar_int_out.cx(), Abar_in.cy() + 0.5 * self.interconnect_width)
self.add_segment_center(self.inv_layer, Abar_int_out.center(), end) self.add_segment_center(self.inv_layer, Abar_int_out.center(), end)

5
compiler/modules/rom_base_array.py
View File

@ -112,7 +112,8 @@ class rom_base_array(bitcell_base_array):
self.cell_inst = {} self.cell_inst = {}
self.cell_list = [] self.cell_list = []
self.current_row = 0 self.current_row = 0
#list of current bitline interconnect nets, starts as the same as the bitline list and is updated when new insts of cells are added # list of current bitline interconnect nets,
# starts as the same as the bitline list and is updated when new insts of cells are added
self.int_bl_list = self.bitline_names[0].copy() self.int_bl_list = self.bitline_names[0].copy()
#When rotated correctly rows are word lines #When rotated correctly rows are word lines
for row in range(self.row_size + 1): for row in range(self.row_size + 1):
@ -151,7 +152,7 @@ class rom_base_array(bitcell_base_array):
# when col = 0, bl_h is connected to precharge, otherwise connect to previous bl connection # when col = 0, bl_h is connected to precharge, otherwise connect to previous bl connection
# when col = col_size - 1 connected column_sizeto gnd otherwise create new bl connection # when col = col_size - 1 connected column_sizeto gnd otherwise create new bl connection
if row == self.row_size : if row == self.row_size:
bl_l = self.int_bl_list[col] bl_l = self.int_bl_list[col]
bl_h = "gnd" bl_h = "gnd"

2
compiler/tests/05_rom_base_bank_2kB_test.py
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@ -1,7 +1,7 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
# See LICENSE for licensing information. # See LICENSE for licensing information.
# #
# Copyright (c) 2016-2021 Regents of the University of California and The Board # Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College # of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University) # (acting for and on behalf of Oklahoma State University)
# All rights reserved. # All rights reserved.