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https://github.com/VLSIDA/OpenRAM.git
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passing code style
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@@ -32,14 +32,14 @@ class rom_precharge_array(design):
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name = "rom_inv_array_{0}".format(cols)
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if strap_spacing != None:
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self.strap_spacing = strap_spacing
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self.strap_spacing = strap_spacing
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else:
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self.strap_spacing = 0
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if strap_spacing != 0:
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self.num_straps = ceil(self.cols / self.strap_spacing)
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self.array_col_size = self.cols + self.num_straps
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self.array_col_size = self.cols + self.num_straps
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else:
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self.num_straps = 0
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self.array_col_size = self.cols
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@@ -54,7 +54,7 @@ class rom_precharge_array(design):
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self.create_instances()
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def create_layout(self):
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self.width = self.cols * self.pmos.width
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self.width = self.cols * self.pmos.width
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self.height = self.pmos.width
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self.place_instances()
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self.create_layout_pins()
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@@ -70,7 +70,7 @@ class rom_precharge_array(design):
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self.add_label(layer="nwell", text="upper right",offset=ur)
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# ur = vector(ur.x, ur.y - self.well_ll.y)
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super().add_boundary(vector(0, 0), ur)
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self.height = ur.y
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self.height = ur.y
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self.width = ur.x
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def create_modules(self):
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@@ -118,8 +118,8 @@ class rom_precharge_array(design):
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self.add_label("ZERO", self.route_layer)
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self.array_pos = []
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strap_num = 0
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cell_y = 0
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strap_num = 0
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cell_y = 0
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# columns are bit lines
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cell_x = 0
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@@ -163,7 +163,7 @@ class rom_precharge_array(design):
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start = vector(tap_pin.cx(), tap_pin.by())
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end = vector(start.x, tap.mod.get_pin("poly_tap").cy())
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self.add_segment_center(layer="poly", start=start, end=end)
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offset_start = vector(end.x - self.poly_tap.width + self.poly_extend_active, end.y)
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offset_start = vector(end.x - self.poly_tap.width + self.poly_extend_active, end.y)
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offset_end = end + vector(0.5*self.poly_width, 0)
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self.add_segment_center(layer="poly", start=offset_start, end=offset_end)
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